blob: 6a9d144512c01dcb34d58517d7fbb94140b22155 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
|
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1996 David S. Miller (dm@sgi.com)
* Compability with board caches, Ulf Carlsson
*/
#include <linux/kernel.h>
#include <asm/sgialib.h>
#include <asm/bcache.h>
/*
* IP22 boardcache is not compatible with board caches. Thus we disable it
* during romvec action. Since r4xx0.c is always compiled and linked with your
* kernel, this shouldn't cause any harm regardless what MIPS processor you
* have.
*
* The ARC write and read functions seem to interfere with the serial lines
* in some way. You should be careful with them.
*/
void prom_putchar(char c)
{
ULONG cnt;
CHAR it = c;
bc_disable();
ArcWrite(1, &it, 1, &cnt);
bc_enable();
}
char prom_getchar(void)
{
ULONG cnt;
CHAR c;
bc_disable();
ArcRead(0, &c, 1, &cnt);
bc_enable();
return c;
}
void prom_printf(char *fmt, ...)
{
va_list args;
char ppbuf[1024];
char *bptr;
va_start(args, fmt);
vsprintf(ppbuf, fmt, args);
bptr = ppbuf;
while (*bptr != 0) {
if (*bptr == '\n')
prom_putchar('\r');
prom_putchar(*bptr++);
}
va_end(args);
}
|
