path: root/arch/arm64/boot/dts/mediatek/mt8183.dtsi

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (c) 2018 MediaTek Inc.
 * Author: Ben Ho <ben.ho@mediatek.com>
 *	   Erin Lo <erin.lo@mediatek.com>
 */

#include <dt-bindings/clock/mt8183-clk.h>
#include <dt-bindings/gce/mt8173-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/memory/mt8183-larb-port.h>
#include <dt-bindings/power/mt8183-power.h>
#include <dt-bindings/reset-controller/mt8183-resets.h>
#include <dt-bindings/phy/phy.h>
#include "mt8183-pinfunc.h"

/ {
	compatible = "mediatek,mt8183";
	interrupt-parent = <&sysirq>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		i2c5 = &i2c5;
		i2c6 = &i2c6;
		i2c7 = &i2c7;
		i2c8 = &i2c8;
		i2c9 = &i2c9;
		i2c10 = &i2c10;
		i2c11 = &i2c11;
		ovl0 = &ovl0;
		ovl-2l0 = &ovl_2l0;
		ovl-2l1 = &ovl_2l1;
		rdma0 = &rdma0;
		rdma1 = &rdma1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};
				core1 {
					cpu = <&cpu5>;
				};
				core2 {
					cpu = <&cpu6>;
				};
				core3 {
					cpu = <&cpu7>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x000>;
			enable-method = "psci";
			capacity-dmips-mhz = <741>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
			dynamic-power-coefficient = <84>;
			#cooling-cells = <2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x001>;
			enable-method = "psci";
			capacity-dmips-mhz = <741>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
			dynamic-power-coefficient = <84>;
			#cooling-cells = <2>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x002>;
			enable-method = "psci";
			capacity-dmips-mhz = <741>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
			dynamic-power-coefficient = <84>;
			#cooling-cells = <2>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x003>;
			enable-method = "psci";
			capacity-dmips-mhz = <741>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
			dynamic-power-coefficient = <84>;
			#cooling-cells = <2>;
		};

		cpu4: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x100>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
			dynamic-power-coefficient = <211>;
			#cooling-cells = <2>;
		};

		cpu5: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x101>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
			dynamic-power-coefficient = <211>;
			#cooling-cells = <2>;
		};

		cpu6: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x102>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
			dynamic-power-coefficient = <211>;
			#cooling-cells = <2>;
		};

		cpu7: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x103>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
			dynamic-power-coefficient = <211>;
			#cooling-cells = <2>;
		};

		idle-states {
			entry-method = "psci";

			CPU_SLEEP: cpu-sleep {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x00010001>;
				entry-latency-us = <200>;
				exit-latency-us = <200>;
				min-residency-us = <800>;
			};

			CLUSTER_SLEEP0: cluster-sleep-0 {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x01010001>;
				entry-latency-us = <250>;
				exit-latency-us = <400>;
				min-residency-us = <1000>;
			};
			CLUSTER_SLEEP1: cluster-sleep-1 {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x01010001>;
				entry-latency-us = <250>;
				exit-latency-us = <400>;
				min-residency-us = <1300>;
			};
		};
	};

	pmu-a53 {
		compatible = "arm,cortex-a53-pmu";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
	};

	pmu-a73 {
		compatible = "arm,cortex-a73-pmu";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
	};

	psci {
		compatible      = "arm,psci-1.0";
		method          = "smc";
	};

	clk26m: oscillator {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
		clock-output-names = "clk26m";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
	};

	soc {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges;

		soc_data: soc_data@8000000 {
			compatible = "mediatek,mt8183-efuse",
				     "mediatek,efuse";
			reg = <0 0x08000000 0 0x0010>;
			#address-cells = <1>;
			#size-cells = <1>;
			status = "disabled";
		};

		gic: interrupt-controller@c000000 {
			compatible = "arm,gic-v3";
			#interrupt-cells = <4>;
			interrupt-parent = <&gic>;
			interrupt-controller;
			reg = <0 0x0c000000 0 0x40000>,  /* GICD */
			      <0 0x0c100000 0 0x200000>, /* GICR */
			      <0 0x0c400000 0 0x2000>,   /* GICC */
			      <0 0x0c410000 0 0x1000>,   /* GICH */
			      <0 0x0c420000 0 0x2000>;   /* GICV */

			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
			ppi-partitions {
				ppi_cluster0: interrupt-partition-0 {
					affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
				};
				ppi_cluster1: interrupt-partition-1 {
					affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
				};
			};
		};

		mcucfg: syscon@c530000 {
			compatible = "mediatek,mt8183-mcucfg", "syscon";
			reg = <0 0x0c530000 0 0x1000>;
			#clock-cells = <1>;
		};

		sysirq: interrupt-controller@c530a80 {
			compatible = "mediatek,mt8183-sysirq",
				     "mediatek,mt6577-sysirq";
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
			reg = <0 0x0c530a80 0 0x50>;
		};

		topckgen: syscon@10000000 {
			compatible = "mediatek,mt8183-topckgen", "syscon";
			reg = <0 0x10000000 0 0x1000>;
			#clock-cells = <1>;
		};

		infracfg: syscon@10001000 {
			compatible = "mediatek,mt8183-infracfg", "syscon";
			reg = <0 0x10001000 0 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		pericfg: syscon@10003000 {
			compatible = "mediatek,mt8183-pericfg", "syscon";
			reg = <0 0x10003000 0 0x1000>;
			#clock-cells = <1>;
		};

		pio: pinctrl@10005000 {
			compatible = "mediatek,mt8183-pinctrl";
			reg = <0 0x10005000 0 0x1000>,
			      <0 0x11f20000 0 0x1000>,
			      <0 0x11e80000 0 0x1000>,
			      <0 0x11e70000 0 0x1000>,
			      <0 0x11e90000 0 0x1000>,
			      <0 0x11d30000 0 0x1000>,
			      <0 0x11d20000 0 0x1000>,
			      <0 0x11c50000 0 0x1000>,
			      <0 0x11f30000 0 0x1000>,
			      <0 0x1000b000 0 0x1000>;
			reg-names = "iocfg0", "iocfg1", "iocfg2",
				    "iocfg3", "iocfg4", "iocfg5",
				    "iocfg6", "iocfg7", "iocfg8",
				    "eint";
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pio 0 0 192>;
			interrupt-controller;
			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
			#interrupt-cells = <2>;
		};

		scpsys: syscon@10006000 {
			compatible = "syscon", "simple-mfd";
			reg = <0 0x10006000 0 0x1000>;
			#power-domain-cells = <1>;

			/* System Power Manager */
			spm: power-controller {
				compatible = "mediatek,mt8183-power-controller";
				#address-cells = <1>;
				#size-cells = <0>;
				#power-domain-cells = <1>;

				/* power domain of the SoC */
				power-domain@MT8183_POWER_DOMAIN_AUDIO {
					reg = <MT8183_POWER_DOMAIN_AUDIO>;
					clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
						 <&infracfg CLK_INFRA_AUDIO>,
						 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>;
					clock-names = "audio", "audio1", "audio2";
					#power-domain-cells = <0>;
				};

				power-domain@MT8183_POWER_DOMAIN_CONN {
					reg = <MT8183_POWER_DOMAIN_CONN>;
					mediatek,infracfg = <&infracfg>;
					#power-domain-cells = <0>;
				};

				power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC {
					reg = <MT8183_POWER_DOMAIN_MFG_ASYNC>;
					clocks =  <&topckgen CLK_TOP_MUX_MFG>;
					clock-names = "mfg";
					#address-cells = <1>;
					#size-cells = <0>;
					#power-domain-cells = <1>;

					mfg: power-domain@MT8183_POWER_DOMAIN_MFG {
						reg = <MT8183_POWER_DOMAIN_MFG>;
						#address-cells = <1>;
						#size-cells = <0>;
						#power-domain-cells = <1>;

						power-domain@MT8183_POWER_DOMAIN_MFG_CORE0 {
							reg = <MT8183_POWER_DOMAIN_MFG_CORE0>;
							#power-domain-cells = <0>;
						};

						power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 {
							reg = <MT8183_POWER_DOMAIN_MFG_CORE1>;
							#power-domain-cells = <0>;
						};

						power-domain@MT8183_POWER_DOMAIN_MFG_2D {
							reg = <MT8183_POWER_DOMAIN_MFG_2D>;
							mediatek,infracfg = <&infracfg>;
							#power-domain-cells = <0>;
						};
					};
				};

				power-domain@MT8183_POWER_DOMAIN_DISP {
					reg = <MT8183_POWER_DOMAIN_DISP>;
					clocks = <&topckgen CLK_TOP_MUX_MM>,
						 <&mmsys CLK_MM_SMI_COMMON>,
						 <&mmsys CLK_MM_SMI_LARB0>,
						 <&mmsys CLK_MM_SMI_LARB1>,
						 <&mmsys CLK_MM_GALS_COMM0>,
						 <&mmsys CLK_MM_GALS_COMM1>,
						 <&mmsys CLK_MM_GALS_CCU2MM>,
						 <&mmsys CLK_MM_GALS_IPU12MM>,
						 <&mmsys CLK_MM_GALS_IMG2MM>,
						 <&mmsys CLK_MM_GALS_CAM2MM>,
						 <&mmsys CLK_MM_GALS_IPU2MM>;
					clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3",
						      "mm-4", "mm-5", "mm-6", "mm-7",
						      "mm-8", "mm-9";
					mediatek,infracfg = <&infracfg>;
					mediatek,smi = <&smi_common>;
					#address-cells = <1>;
					#size-cells = <0>;
					#power-domain-cells = <1>;

					power-domain@MT8183_POWER_DOMAIN_CAM {
						reg = <MT8183_POWER_DOMAIN_CAM>;
						clocks = <&topckgen CLK_TOP_MUX_CAM>,
							 <&camsys CLK_CAM_LARB6>,
							 <&camsys CLK_CAM_LARB3>,
							 <&camsys CLK_CAM_SENINF>,
							 <&camsys CLK_CAM_CAMSV0>,
							 <&camsys CLK_CAM_CAMSV1>,
							 <&camsys CLK_CAM_CAMSV2>,
							 <&camsys CLK_CAM_CCU>;
						clock-names = "cam", "cam-0", "cam-1",
							      "cam-2", "cam-3", "cam-4",
							      "cam-5", "cam-6";
						mediatek,infracfg = <&infracfg>;
						mediatek,smi = <&smi_common>;
						#power-domain-cells = <0>;
					};

					power-domain@MT8183_POWER_DOMAIN_ISP {
						reg = <MT8183_POWER_DOMAIN_ISP>;
						clocks = <&topckgen CLK_TOP_MUX_IMG>,
							 <&imgsys CLK_IMG_LARB5>,
							 <&imgsys CLK_IMG_LARB2>;
						clock-names = "isp", "isp-0", "isp-1";
						mediatek,infracfg = <&infracfg>;
						mediatek,smi = <&smi_common>;
						#power-domain-cells = <0>;
					};

					power-domain@MT8183_POWER_DOMAIN_VDEC {
						reg = <MT8183_POWER_DOMAIN_VDEC>;
						mediatek,smi = <&smi_common>;
						#power-domain-cells = <0>;
					};

					power-domain@MT8183_POWER_DOMAIN_VENC {
						reg = <MT8183_POWER_DOMAIN_VENC>;
						mediatek,smi = <&smi_common>;
						#power-domain-cells = <0>;
					};

					power-domain@MT8183_POWER_DOMAIN_VPU_TOP {
						reg = <MT8183_POWER_DOMAIN_VPU_TOP>;
						clocks = <&topckgen CLK_TOP_MUX_IPU_IF>,
							 <&topckgen CLK_TOP_MUX_DSP>,
							 <&ipu_conn CLK_IPU_CONN_IPU>,
							 <&ipu_conn CLK_IPU_CONN_AHB>,
							 <&ipu_conn CLK_IPU_CONN_AXI>,
							 <&ipu_conn CLK_IPU_CONN_ISP>,
							 <&ipu_conn CLK_IPU_CONN_CAM_ADL>,
							 <&ipu_conn CLK_IPU_CONN_IMG_ADL>;
						clock-names = "vpu", "vpu1", "vpu-0", "vpu-1",
							      "vpu-2", "vpu-3", "vpu-4", "vpu-5";
						mediatek,infracfg = <&infracfg>;
						mediatek,smi = <&smi_common>;
						#address-cells = <1>;
						#size-cells = <0>;
						#power-domain-cells = <1>;

						power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 {
							reg = <MT8183_POWER_DOMAIN_VPU_CORE0>;
							clocks = <&topckgen CLK_TOP_MUX_DSP1>;
							clock-names = "vpu2";
							mediatek,infracfg = <&infracfg>;
							#power-domain-cells = <0>;
						};

						power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 {
							reg = <MT8183_POWER_DOMAIN_VPU_CORE1>;
							clocks = <&topckgen CLK_TOP_MUX_DSP2>;
							clock-names = "vpu3";
							mediatek,infracfg = <&infracfg>;
							#power-domain-cells = <0>;
						};
					};
				};
			};
		};

		watchdog: watchdog@10007000 {
			compatible = "mediatek,mt8183-wdt";
			reg = <0 0x10007000 0 0x100>;
			#reset-cells = <1>;
		};

		apmixedsys: syscon@1000c000 {
			compatible = "mediatek,mt8183-apmixedsys", "syscon";
			reg = <0 0x1000c000 0 0x1000>;
			#clock-cells = <1>;
		};

		pwrap: pwrap@1000d000 {
			compatible = "mediatek,mt8183-pwrap";
			reg = <0 0x1000d000 0 0x1000>;
			reg-names = "pwrap";
			interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
				 <&infracfg CLK_INFRA_PMIC_AP>;
			clock-names = "spi", "wrap";
		};

		scp: scp@10500000 {
			compatible = "mediatek,mt8183-scp";
			reg = <0 0x10500000 0 0x80000>,
			      <0 0x105c0000 0 0x19080>;
			reg-names = "sram", "cfg";
			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&infracfg CLK_INFRA_SCPSYS>;
			clock-names = "main";
			memory-region = <&scp_mem_reserved>;
			status = "disabled";
		};

		systimer: timer@10017000 {
			compatible = "mediatek,mt8183-timer",
				     "mediatek,mt6765-timer";
			reg = <0 0x10017000 0 0x1000>;
			interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&topckgen CLK_TOP_CLK13M>;
			clock-names = "clk13m";
		};

		iommu: iommu@10205000 {
			compatible = "mediatek,mt8183-m4u";
			reg = <0 0x10205000 0 0x1000>;
			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
			mediatek,larbs = <&larb0 &larb1 &larb2 &larb3
					  &larb4 &larb5 &larb6>;
			#iommu-cells = <1>;
		};

		gce: mailbox@10238000 {
			compatible = "mediatek,mt8183-gce";
			reg = <0 0x10238000 0 0x4000>;
			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>;
			#mbox-cells = <2>;
			clocks = <&infracfg CLK_INFRA_GCE>;
			clock-names = "gce";
		};

		auxadc: auxadc@11001000 {
			compatible = "mediatek,mt8183-auxadc",
				     "mediatek,mt8173-auxadc";
			reg = <0 0x11001000 0 0x1000>;
			clocks = <&infracfg CLK_INFRA_AUXADC>;
			clock-names = "main";
			#io-channel-cells = <1>;
			status = "disabled";
		};

		uart0: serial@11002000 {
			compatible = "mediatek,mt8183-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11002000 0 0x1000>;
			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

		uart1: serial@11003000 {
			compatible = "mediatek,mt8183-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11003000 0 0x1000>;
			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

		uart2: serial@11004000 {
			compatible = "mediatek,mt8183-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11004000 0 0x1000>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

		i2c6: i2c@11005000 {
			compatible = "mediatek,mt8183-i2c";
			reg = <0 0x11005000 0 0x1000>,
			      <0 0x11000600 0 0x80>;
			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg CLK_INFRA_I2C6>,
				 <&infracfg CLK_INFRA_AP_DMA>;
			clock-names = "main", "dma";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c0: i2c@11007000 {
			compatible = "mediatek,mt8183-i2c";
			reg = <0 0x11007000 0 0x1000>,
			      <0 0x11000080 0 0x80>;
			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg CLK_INFRA_I2C0>,
				 <&infracfg CLK_INFRA_AP_DMA>;
			clock-names = "main", "dma";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c4: i2c@11008000 {
			compatible = "mediatek,mt8183-i2c";
			reg = <0 0x11008000 0 0x1000>,
			      <0 0x11000100 0 0x80>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg CLK_INFRA_I2C1>,
				 <&infracfg CLK_INFRA_AP_DMA>,
				 <&infracfg CLK_INFRA_I2C1_ARBITER>;
			clock-names = "main", "dma","arb";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c2: i2c@11009000 {
			compatible = "mediatek,mt8183-i2c";
			reg = <0 0x11009000 0 0x1000>,
			      <0 0x11000280 0 0x80>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg CLK_INFRA_I2C2>,
				 <&infracfg CLK_INFRA_AP_DMA>,
				 <&infracfg CLK_INFRA_I2C2_ARBITER>;
			clock-names = "main", "dma", "arb";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi0: spi@1100a000 {
			compatible = "mediatek,mt8183-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0 0x1100a000 0 0x1000>;
			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
				 <&topckgen CLK_TOP_MUX_SPI>,
				 <&infracfg CLK_INFRA_SPI0>;
			clock-names = "parent-clk", "sel-clk", "spi-clk";
			status = "disabled";
		};

		pwm0: pwm@1100e000 {
			compatible = "mediatek,mt8183-disp-pwm";
			reg = <0 0x1100e000 0 0x1000>;
			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			#pwm-cells = <2>;
			clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>,
					<&infracfg CLK_INFRA_DISP_PWM>;
			clock-names = "main", "mm";
		};

		pwm1: pwm@11006000 {
			compatible = "mediatek,mt8183-pwm";
			reg = <0 0x11006000 0 0x1000>;
			#pwm-cells = <2>;
			clocks = <&infracfg CLK_INFRA_PWM>,
				 <&infracfg CLK_INFRA_PWM_HCLK>,
				 <&infracfg CLK_INFRA_PWM1>,
				 <&infracfg CLK_INFRA_PWM2>,
				 <&infracfg CLK_INFRA_PWM3>,
				 <&infracfg CLK_INFRA_PWM4>;
			clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
				      "pwm4";
		};

		i2c3: i2c@1100f000 {
			compatible = "mediatek,mt8183-i2c";
			reg = <0 0x1100f000 0 0x1000>,
			      <0 0x11000400 0 0x80>;
			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg CLK_INFRA_I2C3>,
				 <&infracfg CLK_INFRA_AP_DMA>;
			clock-names = "main", "dma";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi1: spi@11010000 {
			compatible = "mediatek,mt8183-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0 0x11010000 0 0x1000>;
			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
				 <&topckgen CLK_TOP_MUX_SPI>,
				 <&infracfg CLK_INFRA_SPI1>;
			clock-names = "parent-clk", "sel-clk", "spi-clk";
			status = "disabled";
		};

		i2c1: i2c@11011000 {
			compatible = "mediatek,mt8183-i2c";
			reg = <0 0x11011000 0 0x1000>,
			      <0 0x11000480 0 0x80>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg CLK_INFRA_I2C4>,
				 <&infracfg CLK_INFRA_AP_DMA>;
			clock-names = "main", "dma";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi2: spi@11012000 {
			compatible = "mediatek,mt8183-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0 0x11012000 0 0x1000>;
			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
				 <&topckgen CLK_TOP_MUX_SPI>,
				 <&infracfg CLK_INFRA_SPI2>;
			clock-names = "parent-clk", "sel-clk", "spi-clk";
			status = "disabled";
		};

		spi3: spi@11013000 {
			compatible = "mediatek,mt8183-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0 0x11013000 0 0x1000>;
			interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
				 <&topckgen CLK_TOP_MUX_SPI>,
				 <&infracfg CLK_INFRA_SPI3>;
			clock-names = "parent-clk", "sel-clk", "spi-clk";
			status = "disabled";
		};

		i2c9: i2c@11014000 {
			compatible = "mediatek,mt8183-i2c";
			reg = <0 0x11014000 0 0x1000>,
			      <0 0x11000180 0 0x80>;
			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg CLK_INFRA_I2C1_IMM>,
				 <&infracfg CLK_INFRA_AP_DMA>,
				 <&infracfg CLK_INFRA_I2C1_ARBITER>;
			clock-names = "main", "dma", "arb";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c10: i2c@11015000 {
			compatible = "mediatek,mt8183-i2c";
			reg = <0 0x11015000 0 0x1000>,
			      <0 0x11000300 0 0x80>;
			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg CLK_INFRA_I2C2_IMM>,
				 <&infracfg CLK_INFRA_AP_DMA>,
				 <&infracfg CLK_INFRA_I2C2_ARBITER>;
			clock-names = "main", "dma", "arb";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c5: i2c@11016000 {
			compatible = "mediatek,mt8183-i2c";
			reg = <0 0x11016000 0 0x1000>,
			      <0 0x11000500 0 0x80>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg CLK_INFRA_I2C5>,
				 <&infracfg CLK_INFRA_AP_DMA>,
				 <&infracfg CLK_INFRA_I2C5_ARBITER>;
			clock-names = "main", "dma", "arb";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c11: i2c@11017000 {
			compatible = "mediatek,mt8183-i2c";
			reg = <0 0x11017000 0 0x1000>,
			      <0 0x11000580 0 0x80>;
			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg CLK_INFRA_I2C5_IMM>,
				 <&infracfg CLK_INFRA_AP_DMA>,
				 <&infracfg CLK_INFRA_I2C5_ARBITER>;
			clock-names = "main", "dma", "arb";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi4: spi@11018000 {
			compatible = "mediatek,mt8183-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0 0x11018000 0 0x1000>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
				 <&topckgen CLK_TOP_MUX_SPI>,
				 <&infracfg CLK_INFRA_SPI4>;
			clock-names = "parent-clk", "sel-clk", "spi-clk";
			status = "disabled";
		};

		spi5: spi@11019000 {
			compatible = "mediatek,mt8183-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0 0x11019000 0 0x1000>;
			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
				 <&topckgen CLK_TOP_MUX_SPI>,
				 <&infracfg CLK_INFRA_SPI5>;
			clock-names = "parent-clk", "sel-clk", "spi-clk";
			status = "disabled";
		};

		i2c7: i2c@1101a000 {
			compatible = "mediatek,mt8183-i2c";
			reg = <0 0x1101a000 0 0x1000>,
			      <0 0x11000680 0 0x80>;
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg CLK_INFRA_I2C7>,
				 <&infracfg CLK_INFRA_AP_DMA>;
			clock-names = "main", "dma";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c8: i2c@1101b000 {
			compatible = "mediatek,mt8183-i2c";
			reg = <0 0x1101b000 0 0x1000>,
			      <0 0x11000700 0 0x80>;
			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg CLK_INFRA_I2C8>,
				 <&infracfg CLK_INFRA_AP_DMA>;
			clock-names = "main", "dma";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		ssusb: usb@11201000 {
			compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3";
			reg = <0 0x11201000 0 0x2e00>,
			      <0 0x11203e00 0 0x0100>;
			reg-names = "mac", "ippc";
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
			phys = <&u2port0 PHY_TYPE_USB2>,
			       <&u3port0 PHY_TYPE_USB3>;
			clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
				 <&infracfg CLK_INFRA_USB>;
			clock-names = "sys_ck", "ref_ck";
			mediatek,syscon-wakeup = <&pericfg 0x400 0>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			status = "disabled";

			usb_host: xhci@11200000 {
				compatible = "mediatek,mt8183-xhci",
					     "mediatek,mtk-xhci";
				reg = <0 0x11200000 0 0x1000>;
				reg-names = "mac";
				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
				clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
					 <&infracfg CLK_INFRA_USB>;
				clock-names = "sys_ck", "ref_ck";
				status = "disabled";
			};
		};

		audiosys: syscon@11220000 {
			compatible = "mediatek,mt8183-audiosys", "syscon";
			reg = <0 0x11220000 0 0x1000>;
			#clock-cells = <1>;
		};

		mmc0: mmc@11230000 {
			compatible = "mediatek,mt8183-mmc";
			reg = <0 0x11230000 0 0x1000>,
			      <0 0x11f50000 0 0x1000>;
			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>,
				 <&infracfg CLK_INFRA_MSDC0>,
				 <&infracfg CLK_INFRA_MSDC0_SCK>;
			clock-names = "source", "hclk", "source_cg";
			status = "disabled";
		};

		mmc1: mmc@11240000 {
			compatible = "mediatek,mt8183-mmc";
			reg = <0 0x11240000 0 0x1000>,
			      <0 0x11e10000 0 0x1000>;
			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>,
				 <&infracfg CLK_INFRA_MSDC1>,
				 <&infracfg CLK_INFRA_MSDC1_SCK>;
			clock-names = "source", "hclk", "source_cg";
			status = "disabled";
		};

		mipi_tx0: mipi-dphy@11e50000 {
			compatible = "mediatek,mt8183-mipi-tx";
			reg = <0 0x11e50000 0 0x1000>;
			clocks = <&apmixedsys CLK_APMIXED_MIPID0_26M>;
			clock-names = "ref_clk";
			#clock-cells = <0>;
			#phy-cells = <0>;
			clock-output-names = "mipi_tx0_pll";
			nvmem-cells = <&mipi_tx_calibration>;
			nvmem-cell-names = "calibration-data";
		};

		efuse: efuse@11f10000 {
			compatible = "mediatek,mt8183-efuse",
				     "mediatek,efuse";
			reg = <0 0x11f10000 0 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			mipi_tx_calibration: calib@190 {
				reg = <0x190 0xc>;
			};
		};

		u3phy: usb-phy@11f40000 {
			compatible = "mediatek,mt8183-tphy",
				     "mediatek,generic-tphy-v2";
			#address-cells = <1>;
			#phy-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0x11f40000 0x1000>;
			status = "okay";

			u2port0: usb-phy@0 {
				reg = <0x0 0x700>;
				clocks = <&clk26m>;
				clock-names = "ref";
				#phy-cells = <1>;
				mediatek,discth = <15>;
				status = "okay";
			};

			u3port0: usb-phy@0700 {
				reg = <0x0700 0x900>;
				clocks = <&clk26m>;
				clock-names = "ref";
				#phy-cells = <1>;
				status = "okay";
			};
		};

		mfgcfg: syscon@13000000 {
			compatible = "mediatek,mt8183-mfgcfg", "syscon";
			reg = <0 0x13000000 0 0x1000>;
			#clock-cells = <1>;
		};

		mmsys: syscon@14000000 {
			compatible = "mediatek,mt8183-mmsys", "syscon";
			reg = <0 0x14000000 0 0x1000>;
			#clock-cells = <1>;
		};

		ovl0: ovl@14008000 {
			compatible = "mediatek,mt8183-disp-ovl";
			reg = <0 0x14008000 0 0x1000>;
			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			clocks = <&mmsys CLK_MM_DISP_OVL0>;
			iommus = <&iommu M4U_PORT_DISP_OVL0>;
			mediatek,larb = <&larb0>;
			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
		};

		ovl_2l0: ovl@14009000 {
			compatible = "mediatek,mt8183-disp-ovl-2l";
			reg = <0 0x14009000 0 0x1000>;
			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
			iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
			mediatek,larb = <&larb0>;
			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
		};

		ovl_2l1: ovl@1400a000 {
			compatible = "mediatek,mt8183-disp-ovl-2l";
			reg = <0 0x1400a000 0 0x1000>;
			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
			iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>;
			mediatek,larb = <&larb0>;
			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
		};

		rdma0: rdma@1400b000 {
			compatible = "mediatek,mt8183-disp-rdma";
			reg = <0 0x1400b000 0 0x1000>;
			interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
			iommus = <&iommu M4U_PORT_DISP_RDMA0>;
			mediatek,larb = <&larb0>;
			mediatek,rdma-fifo-size = <5120>;
			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
		};

		rdma1: rdma@1400c000 {
			compatible = "mediatek,mt8183-disp-rdma";
			reg = <0 0x1400c000 0 0x1000>;
			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
			iommus = <&iommu M4U_PORT_DISP_RDMA1>;
			mediatek,larb = <&larb0>;
			mediatek,rdma-fifo-size = <2048>;
			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
		};

		color0: color@1400e000 {
			compatible = "mediatek,mt8183-disp-color",
				     "mediatek,mt8173-disp-color";
			reg = <0 0x1400e000 0 0x1000>;
			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
		};

		ccorr0: ccorr@1400f000 {
			compatible = "mediatek,mt8183-disp-ccorr";
			reg = <0 0x1400f000 0 0x1000>;
			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
		};

		aal0: aal@14010000 {
			compatible = "mediatek,mt8183-disp-aal",
				     "mediatek,mt8173-disp-aal";
			reg = <0 0x14010000 0 0x1000>;
			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			clocks = <&mmsys CLK_MM_DISP_AAL0>;
		};

		gamma0: gamma@14011000 {
			compatible = "mediatek,mt8183-disp-gamma";
			reg = <0 0x14011000 0 0x1000>;
			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
		};

		dither0: dither@14012000 {
			compatible = "mediatek,mt8183-disp-dither";
			reg = <0 0x14012000 0 0x1000>;
			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
		};

		dsi0: dsi@14014000 {
			compatible = "mediatek,mt8183-dsi";
			reg = <0 0x14014000 0 0x1000>;
			interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			mediatek,syscon-dsi = <&mmsys 0x140>;
			clocks = <&mmsys CLK_MM_DSI0_MM>,
				 <&mmsys CLK_MM_DSI0_IF>,
				 <&mipi_tx0>;
			clock-names = "engine", "digital", "hs";
			phys = <&mipi_tx0>;
			phy-names = "dphy";
		};

		mutex: mutex@14016000 {
			compatible = "mediatek,mt8183-disp-mutex";
			reg = <0 0x14016000 0 0x1000>;
			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
		};

		larb0: larb@14017000 {
			compatible = "mediatek,mt8183-smi-larb";
			reg = <0 0x14017000 0 0x1000>;
			mediatek,smi = <&smi_common>;
			clocks = <&mmsys CLK_MM_SMI_LARB0>,
				 <&mmsys CLK_MM_SMI_LARB0>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			clock-names = "apb", "smi";
		};

		smi_common: smi@14019000 {
			compatible = "mediatek,mt8183-smi-common", "syscon";
			reg = <0 0x14019000 0 0x1000>;
			clocks = <&mmsys CLK_MM_SMI_COMMON>,
				 <&mmsys CLK_MM_SMI_COMMON>,
				 <&mmsys CLK_MM_GALS_COMM0>,
				 <&mmsys CLK_MM_GALS_COMM1>;
			clock-names = "apb", "smi", "gals0", "gals1";
		};

		imgsys: syscon@15020000 {
			compatible = "mediatek,mt8183-imgsys", "syscon";
			reg = <0 0x15020000 0 0x1000>;
			#clock-cells = <1>;
		};

		larb5: larb@15021000 {
			compatible = "mediatek,mt8183-smi-larb";
			reg = <0 0x15021000 0 0x1000>;
			mediatek,smi = <&smi_common>;
			clocks = <&imgsys CLK_IMG_LARB5>, <&imgsys CLK_IMG_LARB5>,
				 <&mmsys CLK_MM_GALS_IMG2MM>;
			clock-names = "apb", "smi", "gals";
			power-domains = <&spm MT8183_POWER_DOMAIN_ISP>;
		};

		larb2: larb@1502f000 {
			compatible = "mediatek,mt8183-smi-larb";
			reg = <0 0x1502f000 0 0x1000>;
			mediatek,smi = <&smi_common>;
			clocks = <&imgsys CLK_IMG_LARB2>, <&imgsys CLK_IMG_LARB2>,
				 <&mmsys CLK_MM_GALS_IPU2MM>;
			clock-names = "apb", "smi", "gals";
			power-domains = <&spm MT8183_POWER_DOMAIN_ISP>;
		};

		vdecsys: syscon@16000000 {
			compatible = "mediatek,mt8183-vdecsys", "syscon";
			reg = <0 0x16000000 0 0x1000>;
			#clock-cells = <1>;
		};

		larb1: larb@16010000 {
			compatible = "mediatek,mt8183-smi-larb";
			reg = <0 0x16010000 0 0x1000>;
			mediatek,smi = <&smi_common>;
			clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LARB1>;
			clock-names = "apb", "smi";
			power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>;
		};

		vencsys: syscon@17000000 {
			compatible = "mediatek,mt8183-vencsys", "syscon";
			reg = <0 0x17000000 0 0x1000>;
			#clock-cells = <1>;
		};

		larb4: larb@17010000 {
			compatible = "mediatek,mt8183-smi-larb";
			reg = <0 0x17010000 0 0x1000>;
			mediatek,smi = <&smi_common>;
			clocks = <&vencsys CLK_VENC_LARB>,
				 <&vencsys CLK_VENC_LARB>;
			clock-names = "apb", "smi";
			power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
		};

		ipu_conn: syscon@19000000 {
			compatible = "mediatek,mt8183-ipu_conn", "syscon";
			reg = <0 0x19000000 0 0x1000>;
			#clock-cells = <1>;
		};

		ipu_adl: syscon@19010000 {
			compatible = "mediatek,mt8183-ipu_adl", "syscon";
			reg = <0 0x19010000 0 0x1000>;
			#clock-cells = <1>;
		};

		ipu_core0: syscon@19180000 {
			compatible = "mediatek,mt8183-ipu_core0", "syscon";
			reg = <0 0x19180000 0 0x1000>;
			#clock-cells = <1>;
		};

		ipu_core1: syscon@19280000 {
			compatible = "mediatek,mt8183-ipu_core1", "syscon";
			reg = <0 0x19280000 0 0x1000>;
			#clock-cells = <1>;
		};

		camsys: syscon@1a000000 {
			compatible = "mediatek,mt8183-camsys", "syscon";
			reg = <0 0x1a000000 0 0x1000>;
			#clock-cells = <1>;
		};

		larb6: larb@1a001000 {
			compatible = "mediatek,mt8183-smi-larb";
			reg = <0 0x1a001000 0 0x1000>;
			mediatek,smi = <&smi_common>;
			clocks = <&camsys CLK_CAM_LARB6>, <&camsys CLK_CAM_LARB6>,
				 <&mmsys CLK_MM_GALS_CAM2MM>;
			clock-names = "apb", "smi", "gals";
			power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
		};

		larb3: larb@1a002000 {
			compatible = "mediatek,mt8183-smi-larb";
			reg = <0 0x1a002000 0 0x1000>;
			mediatek,smi = <&smi_common>;
			clocks = <&camsys CLK_CAM_LARB3>, <&camsys CLK_CAM_LARB3>,
				 <&mmsys CLK_MM_GALS_IPU12MM>;
			clock-names = "apb", "smi", "gals";
			power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
		};
	};
};