1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
|
/*
* R-Car Generation 2 Power management support
*
* Copyright (C) 2013 - 2015 Renesas Electronics Corporation
* Copyright (C) 2011 Renesas Solutions Corp.
* Copyright (C) 2011 Magnus Damm
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/smp.h>
#include <linux/soc/renesas/rcar-sysc.h>
#include <asm/io.h>
#include "common.h"
#include "rcar-gen2.h"
/* RST */
#define RST 0xe6160000
#define CA15BAR 0x0020 /* CA15 Boot Address Register */
#define CA7BAR 0x0030 /* CA7 Boot Address Register */
#define CA15RESCNT 0x0040 /* CA15 Reset Control Register */
#define CA7RESCNT 0x0044 /* CA7 Reset Control Register */
/* SYS Boot Address Register */
#define SBAR_BAREN BIT(4) /* SBAR is valid */
/* Reset Control Registers */
#define CA15RESCNT_CODE 0xa5a50000
#define CA15RESCNT_CPUS 0xf /* CPU0-3 */
#define CA7RESCNT_CODE 0x5a5a0000
#define CA7RESCNT_CPUS 0xf /* CPU0-3 */
/* On-chip RAM */
#define ICRAM1 0xe63c0000 /* Inter Connect RAM1 (4 KiB) */
static inline u32 phys_to_sbar(phys_addr_t addr)
{
return (addr >> 8) & 0xfffffc00;
}
/* SYSC */
#define SYSCIER 0x0c
#define SYSCIMR 0x10
#if defined(CONFIG_SMP)
static void __init rcar_gen2_sysc_init(u32 syscier)
{
rcar_sysc_init(0xe6180000, syscier);
}
#else /* CONFIG_SMP */
static inline void rcar_gen2_sysc_init(u32 syscier) {}
#endif /* CONFIG_SMP */
void __init rcar_gen2_pm_init(void)
{
void __iomem *p;
u32 bar;
static int once;
struct device_node *np, *cpus;
bool has_a7 = false;
bool has_a15 = false;
phys_addr_t boot_vector_addr = ICRAM1;
u32 syscier = 0;
if (once++)
return;
cpus = of_find_node_by_path("/cpus");
if (!cpus)
return;
for_each_child_of_node(cpus, np) {
if (of_device_is_compatible(np, "arm,cortex-a15"))
has_a15 = true;
else if (of_device_is_compatible(np, "arm,cortex-a7"))
has_a7 = true;
}
if (of_machine_is_compatible("renesas,r8a7790"))
syscier = 0x013111ef;
else if (of_machine_is_compatible("renesas,r8a7791"))
syscier = 0x00111003;
/* RAM for jump stub, because BAR requires 256KB aligned address */
p = ioremap_nocache(boot_vector_addr, shmobile_boot_size);
memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
iounmap(p);
/* setup reset vectors */
p = ioremap_nocache(RST, 0x63);
bar = phys_to_sbar(boot_vector_addr);
if (has_a15) {
writel_relaxed(bar, p + CA15BAR);
writel_relaxed(bar | SBAR_BAREN, p + CA15BAR);
/* de-assert reset for CA15 CPUs */
writel_relaxed((readl_relaxed(p + CA15RESCNT) &
~CA15RESCNT_CPUS) | CA15RESCNT_CODE,
p + CA15RESCNT);
}
if (has_a7) {
writel_relaxed(bar, p + CA7BAR);
writel_relaxed(bar | SBAR_BAREN, p + CA7BAR);
/* de-assert reset for CA7 CPUs */
writel_relaxed((readl_relaxed(p + CA7RESCNT) &
~CA7RESCNT_CPUS) | CA7RESCNT_CODE,
p + CA7RESCNT);
}
iounmap(p);
rcar_gen2_sysc_init(syscier);
shmobile_smp_apmu_suspend_init();
}
|
