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|
/*
* Copyright (C) 2012 STMicroelectronics Limited.
* Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
#include "stih41x.dtsi"
#include "stih416-clock.dtsi"
#include "stih416-pinctrl.dtsi"
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/stih416-resets.h>
#include <dt-bindings/interrupt-controller/irq-st.h>
/ {
L2: cache-controller {
compatible = "arm,pl310-cache";
reg = <0xfffe2000 0x1000>;
arm,data-latency = <3 3 3>;
arm,tag-latency = <2 2 2>;
cache-unified;
cache-level = <2>;
};
arm-pmu {
compatible = "arm,cortex-a9-pmu";
interrupt-parent = <&intc>;
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
ranges;
compatible = "simple-bus";
restart {
compatible = "st,stih416-restart";
st,syscfg = <&syscfg_sbc>;
status = "okay";
};
powerdown: powerdown-controller {
#reset-cells = <1>;
compatible = "st,stih416-powerdown";
};
softreset: softreset-controller {
#reset-cells = <1>;
compatible = "st,stih416-softreset";
};
syscfg_sbc:sbc-syscfg@fe600000{
compatible = "st,stih416-sbc-syscfg", "syscon";
reg = <0xfe600000 0x1000>;
};
syscfg_front:front-syscfg@fee10000{
compatible = "st,stih416-front-syscfg", "syscon";
reg = <0xfee10000 0x1000>;
};
syscfg_rear:rear-syscfg@fe830000{
compatible = "st,stih416-rear-syscfg", "syscon";
reg = <0xfe830000 0x1000>;
};
/* MPE */
syscfg_fvdp_fe:fvdp-fe-syscfg@fddf0000{
compatible = "st,stih416-fvdp-fe-syscfg", "syscon";
reg = <0xfddf0000 0x1000>;
};
syscfg_fvdp_lite:fvdp-lite-syscfg@fd6a0000{
compatible = "st,stih416-fvdp-lite-syscfg", "syscon";
reg = <0xfd6a0000 0x1000>;
};
syscfg_cpu:cpu-syscfg@fdde0000{
compatible = "st,stih416-cpu-syscfg", "syscon";
reg = <0xfdde0000 0x1000>;
};
syscfg_compo:compo-syscfg@fd320000{
compatible = "st,stih416-compo-syscfg", "syscon";
reg = <0xfd320000 0x1000>;
};
syscfg_transport:transport-syscfg@fd690000{
compatible = "st,stih416-transport-syscfg", "syscon";
reg = <0xfd690000 0x1000>;
};
syscfg_lpm:lpm-syscfg@fe4b5100{
compatible = "st,stih416-lpm-syscfg", "syscon";
reg = <0xfe4b5100 0x8>;
};
irq-syscfg {
compatible = "st,stih416-irq-syscfg";
st,syscfg = <&syscfg_cpu>;
st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
<ST_IRQ_SYSCFG_PMU_1>;
st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
<ST_IRQ_SYSCFG_DISABLED>;
};
serial2: serial@fed32000{
compatible = "st,asc";
status = "disabled";
reg = <0xfed32000 0x2c>;
interrupts = <0 197 0>;
clocks = <&clk_s_a0_ls CLK_ICN_REG>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_serial2 &pinctrl_serial2_oe>;
};
/* SBC_UART1 */
sbc_serial1: serial@fe531000 {
compatible = "st,asc";
status = "disabled";
reg = <0xfe531000 0x2c>;
interrupts = <0 210 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sbc_serial1>;
clocks = <&clk_sysin>;
};
i2c@fed40000 {
compatible = "st,comms-ssc4-i2c";
reg = <0xfed40000 0x110>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_s_a0_ls CLK_ICN_REG>;
clock-names = "ssc";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0_default>;
status = "disabled";
};
i2c@fed41000 {
compatible = "st,comms-ssc4-i2c";
reg = <0xfed41000 0x110>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_s_a0_ls CLK_ICN_REG>;
clock-names = "ssc";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_default>;
status = "disabled";
};
i2c@fe540000 {
compatible = "st,comms-ssc4-i2c";
reg = <0xfe540000 0x110>;
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_sysin>;
clock-names = "ssc";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sbc_i2c0_default>;
status = "disabled";
};
i2c@fe541000 {
compatible = "st,comms-ssc4-i2c";
reg = <0xfe541000 0x110>;
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_sysin>;
clock-names = "ssc";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sbc_i2c1_default>;
status = "disabled";
};
ethernet0: dwmac@fe810000 {
device_type = "network";
compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
status = "disabled";
reg = <0xfe810000 0x8000>;
reg-names = "stmmaceth";
interrupts = <0 133 0>, <0 134 0>, <0 135 0>;
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
snps,pbl = <32>;
snps,mixed-burst;
st,syscon = <&syscfg_rear 0x8bc>;
resets = <&softreset STIH416_ETH0_SOFTRESET>;
reset-names = "stmmaceth";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mii0>;
clock-names = "stmmaceth", "sti-ethclk";
clocks = <&clk_s_a1_ls CLK_ICN_IF_2>, <&clk_s_a1_ls CLK_GMAC0_PHY>;
};
ethernet1: dwmac@fef08000 {
device_type = "network";
compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
status = "disabled";
reg = <0xfef08000 0x8000>;
reg-names = "stmmaceth";
interrupts = <0 136 0>, <0 137 0>, <0 138 0>;
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
snps,pbl = <32>;
snps,mixed-burst;
st,syscon = <&syscfg_sbc 0x7f0>;
resets = <&softreset STIH416_ETH1_SOFTRESET>;
reset-names = "stmmaceth";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mii1>;
clock-names = "stmmaceth", "sti-ethclk";
clocks = <&clk_s_a0_ls CLK_ICN_REG>, <&clk_s_a0_ls CLK_ETH1_PHY>;
};
rc: rc@fe518000 {
compatible = "st,comms-irb";
reg = <0xfe518000 0x234>;
interrupts = <0 203 0>;
rx-mode = "infrared";
clocks = <&clk_sysin>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ir>;
resets = <&softreset STIH416_IRB_SOFTRESET>;
};
/* FSM */
spifsm: spifsm@fe902000 {
compatible = "st,spi-fsm";
reg = <0xfe902000 0x1000>;
pinctrl-0 = <&pinctrl_fsm>;
st,syscfg = <&syscfg_rear>;
st,boot-device-reg = <0x958>;
st,boot-device-spi = <0x1a>;
status = "disabled";
};
keyscan: keyscan@fe4b0000 {
compatible = "st,sti-keyscan";
status = "disabled";
reg = <0xfe4b0000 0x2000>;
interrupts = <GIC_SPI 212 IRQ_TYPE_NONE>;
clocks = <&clk_sysin>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_keyscan>;
resets = <&powerdown STIH416_KEYSCAN_POWERDOWN>,
<&softreset STIH416_KEYSCAN_SOFTRESET>;
};
temp0 {
compatible = "st,stih416-sas-thermal";
clock-names = "thermal";
clocks = <&clockgen_c_vcc 14>;
status = "okay";
};
temp1@fdfe8000 {
compatible = "st,stih416-mpe-thermal";
reg = <0xfdfe8000 0x10>;
clocks = <&clockgen_e 3>;
clock-names = "thermal";
interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
status = "okay";
};
mmc0: sdhci@fe81e000 {
compatible = "st,sdhci";
status = "disabled";
reg = <0xfe81e000 0x1000>;
interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>;
interrupt-names = "mmcirq";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc0>;
clock-names = "mmc";
clocks = <&clk_s_a1_ls 1>;
};
mmc1: sdhci@fe81f000 {
compatible = "st,sdhci";
status = "disabled";
reg = <0xfe81f000 0x1000>;
interrupts = <GIC_SPI 128 IRQ_TYPE_NONE>;
interrupt-names = "mmcirq";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc1>;
clock-names = "mmc";
clocks = <&clk_s_a1_ls 8>;
};
miphy365x_phy: phy@fe382000 {
compatible = "st,miphy365x-phy";
st,syscfg = <&syscfg_rear 0x824 0x828>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
phy_port0: port@fe382000 {
#phy-cells = <1>;
reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
reg-names = "sata", "pcie";
};
phy_port1: port@fe38a000 {
#phy-cells = <1>;
reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;
reg-names = "sata", "pcie";
};
};
sata0: sata@fe380000 {
compatible = "st,sti-ahci";
reg = <0xfe380000 0x1000>;
interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
interrupt-names = "hostc";
phys = <&phy_port0 PHY_TYPE_SATA>;
phy-names = "sata-phy";
resets = <&powerdown STIH416_SATA0_POWERDOWN>,
<&softreset STIH416_SATA0_SOFTRESET>;
reset-names = "pwr-dwn", "sw-rst";
clock-names = "ahci_clk";
clocks = <&clk_s_a0_ls CLK_ICN_REG>;
status = "disabled";
};
usb2_phy: phy@0 {
compatible = "st,stih416-usb-phy";
#phy-cells = <0>;
st,syscfg = <&syscfg_rear>;
clocks = <&clk_sysin>;
clock-names = "osc_phy";
};
ehci0: usb@fe1ffe00 {
compatible = "st,st-ehci-300x";
reg = <0xfe1ffe00 0x100>;
interrupts = <GIC_SPI 148 IRQ_TYPE_NONE>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
clocks = <&clk_s_a1_ls 0>,
<&clockgen_b0 0>;
clock-names = "ic", "clk48";
phys = <&usb2_phy>;
phy-names = "usb";
resets = <&powerdown STIH416_USB0_POWERDOWN>,
<&softreset STIH416_USB0_SOFTRESET>;
reset-names = "power", "softreset";
};
ohci0: usb@fe1ffc00 {
compatible = "st,st-ohci-300x";
reg = <0xfe1ffc00 0x100>;
interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>;
clocks = <&clk_s_a1_ls 0>,
<&clockgen_b0 0>;
clock-names = "ic", "clk48";
phys = <&usb2_phy>;
phy-names = "usb";
status = "okay";
resets = <&powerdown STIH416_USB0_POWERDOWN>,
<&softreset STIH416_USB0_SOFTRESET>;
reset-names = "power", "softreset";
};
ehci1: usb@fe203e00 {
compatible = "st,st-ehci-300x";
reg = <0xfe203e00 0x100>;
interrupts = <GIC_SPI 150 IRQ_TYPE_NONE>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
clocks = <&clk_s_a1_ls 0>,
<&clockgen_b0 0>;
clock-names = "ic", "clk48";
phys = <&usb2_phy>;
phy-names = "usb";
resets = <&powerdown STIH416_USB1_POWERDOWN>,
<&softreset STIH416_USB1_SOFTRESET>;
reset-names = "power", "softreset";
};
ohci1: usb@fe203c00 {
compatible = "st,st-ohci-300x";
reg = <0xfe203c00 0x100>;
interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
clocks = <&clk_s_a1_ls 0>,
<&clockgen_b0 0>;
clock-names = "ic", "clk48";
phys = <&usb2_phy>;
phy-names = "usb";
resets = <&powerdown STIH416_USB1_POWERDOWN>,
<&softreset STIH416_USB1_SOFTRESET>;
reset-names = "power", "softreset";
};
ehci2: usb@fe303e00 {
compatible = "st,st-ehci-300x";
reg = <0xfe303e00 0x100>;
interrupts = <GIC_SPI 152 IRQ_TYPE_NONE>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
clocks = <&clk_s_a1_ls 0>,
<&clockgen_b0 0>;
clock-names = "ic", "clk48";
phys = <&usb2_phy>;
phy-names = "usb";
resets = <&powerdown STIH416_USB2_POWERDOWN>,
<&softreset STIH416_USB2_SOFTRESET>;
reset-names = "power", "softreset";
};
ohci2: usb@fe303c00 {
compatible = "st,st-ohci-300x";
reg = <0xfe303c00 0x100>;
interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
clocks = <&clk_s_a1_ls 0>,
<&clockgen_b0 0>;
clock-names = "ic", "clk48";
phys = <&usb2_phy>;
phy-names = "usb";
resets = <&powerdown STIH416_USB2_POWERDOWN>,
<&softreset STIH416_USB2_SOFTRESET>;
reset-names = "power", "softreset";
};
ehci3: usb@fe343e00 {
compatible = "st,st-ehci-300x";
reg = <0xfe343e00 0x100>;
interrupts = <GIC_SPI 154 IRQ_TYPE_NONE>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb3>;
clocks = <&clk_s_a1_ls 0>,
<&clockgen_b0 0>;
clock-names = "ic", "clk48";
phys = <&usb2_phy>;
phy-names = "usb";
resets = <&powerdown STIH416_USB3_POWERDOWN>,
<&softreset STIH416_USB3_SOFTRESET>;
reset-names = "power", "softreset";
};
ohci3: usb@fe343c00 {
compatible = "st,st-ohci-300x";
reg = <0xfe343c00 0x100>;
interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
clocks = <&clk_s_a1_ls 0>,
<&clockgen_b0 0>;
clock-names = "ic", "clk48";
phys = <&usb2_phy>;
phy-names = "usb";
resets = <&powerdown STIH416_USB3_POWERDOWN>,
<&softreset STIH416_USB3_SOFTRESET>;
reset-names = "power", "softreset";
};
/* SAS PWM Module */
pwm0: pwm@fed10000 {
compatible = "st,sti-pwm";
status = "disabled";
#pwm-cells = <2>;
reg = <0xfed10000 0x68>;
interrupts = <GIC_SPI 200 IRQ_TYPE_NONE>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_chan0_default
&pinctrl_pwm0_chan1_default
&pinctrl_pwm0_chan2_default
&pinctrl_pwm0_chan3_default>;
clock-names = "pwm", "capture";
clocks = <&clk_sysin>, <&clk_s_a0_ls CLK_ICN_REG>;
st,pwm-num-chan = <4>;
st,capture-num-chan = <2>;
};
/* SBC PWM Module */
pwm1: pwm@fe510000 {
compatible = "st,sti-pwm";
status = "disabled";
#pwm-cells = <2>;
reg = <0xfe510000 0x68>;
interrupts = <GIC_SPI 202 IRQ_TYPE_NONE>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1_chan0_default
/*
* Shared with SBC_OBS_NOTRST. Don't
* enable unless you really know what
* you're doing.
*
* &pinctrl_pwm1_chan1_default
*/
&pinctrl_pwm1_chan2_default
&pinctrl_pwm1_chan3_default>;
clock-names = "pwm";
clocks = <&clk_sysin>;
st,pwm-num-chan = <3>;
};
};
};
|
