1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
|
/*
* Copyright (c) 2013-2014 Linaro Ltd.
* Copyright (c) 2013-2014 Hisilicon Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
#include "skeleton.dtsi"
#include <dt-bindings/clock/hix5hd2-clock.h>
/ {
aliases {
serial0 = &uart0;
};
gic: interrupt-controller@f8a01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
/* gic dist base, gic cpu base */
reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges = <0 0xf8000000 0x8000000>;
amba {
#address-cells = <1>;
#size-cells = <1>;
compatible = "arm,amba-bus";
ranges;
timer0: timer@00002000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00002000 0x1000>;
/* timer00 & timer01 */
interrupts = <0 24 4>;
clocks = <&clock HIX5HD2_FIXED_24M>;
status = "disabled";
};
timer1: timer@00a29000 {
/*
* Only used in NORMAL state, not available ins
* SLOW or DOZE state.
* The rate is fixed in 24MHz.
*/
compatible = "arm,sp804", "arm,primecell";
reg = <0x00a29000 0x1000>;
/* timer10 & timer11 */
interrupts = <0 25 4>;
clocks = <&clock HIX5HD2_FIXED_24M>;
status = "disabled";
};
timer2: timer@00a2a000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00a2a000 0x1000>;
/* timer20 & timer21 */
interrupts = <0 26 4>;
clocks = <&clock HIX5HD2_FIXED_24M>;
status = "disabled";
};
timer3: timer@00a2b000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00a2b000 0x1000>;
/* timer30 & timer31 */
interrupts = <0 27 4>;
clocks = <&clock HIX5HD2_FIXED_24M>;
status = "disabled";
};
timer4: timer@00a81000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00a81000 0x1000>;
/* timer30 & timer31 */
interrupts = <0 28 4>;
clocks = <&clock HIX5HD2_FIXED_24M>;
status = "disabled";
};
uart0: uart@00b00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x00b00000 0x1000>;
interrupts = <0 49 4>;
clocks = <&clock HIX5HD2_FIXED_83M>;
clock-names = "apb_pclk";
status = "disabled";
};
uart1: uart@00006000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x00006000 0x1000>;
interrupts = <0 50 4>;
clocks = <&clock HIX5HD2_FIXED_83M>;
clock-names = "apb_pclk";
status = "disabled";
};
uart2: uart@00b02000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x00b02000 0x1000>;
interrupts = <0 51 4>;
clocks = <&clock HIX5HD2_FIXED_83M>;
clock-names = "apb_pclk";
status = "disabled";
};
uart3: uart@00b03000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x00b03000 0x1000>;
interrupts = <0 52 4>;
clocks = <&clock HIX5HD2_FIXED_83M>;
clock-names = "apb_pclk";
status = "disabled";
};
uart4: uart@00b04000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb04000 0x1000>;
interrupts = <0 53 4>;
clocks = <&clock HIX5HD2_FIXED_83M>;
clock-names = "apb_pclk";
status = "disabled";
};
};
local_timer@00a00600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x00a00600 0x20>;
interrupts = <1 13 0xf01>;
};
l2: l2-cache {
compatible = "arm,pl310-cache";
reg = <0x00a10000 0x100000>;
interrupts = <0 15 4>;
cache-unified;
cache-level = <2>;
};
sysctrl: system-controller@00000000 {
compatible = "hisilicon,sysctrl";
reg = <0x00000000 0x1000>;
reboot-offset = <0x4>;
};
cpuctrl@00a22000 {
compatible = "hisilicon,cpuctrl";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x00a22000 0x2000>;
ranges = <0 0x00a22000 0x2000>;
clock: clock@0 {
compatible = "hisilicon,hix5hd2-clock";
reg = <0 0x2000>;
#clock-cells = <1>;
};
};
gmac0: ethernet@1840000 {
compatible = "hisilicon,hix5hd2-gmac";
reg = <0x1840000 0x1000>,<0x184300c 0x4>;
interrupts = <0 71 4>;
clocks = <&clock HIX5HD2_MAC0_CLK>;
status = "disabled";
};
gmac1: ethernet@1841000 {
compatible = "hisilicon,hix5hd2-gmac";
reg = <0x1841000 0x1000>,<0x1843010 0x4>;
interrupts = <0 72 4>;
clocks = <&clock HIX5HD2_MAC1_CLK>;
status = "disabled";
};
};
};
|
