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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SiFive SPI controller
maintainers:
- Pragnesh Patel <pragnesh.patel@sifive.com>
- Paul Walmsley <paul.walmsley@sifive.com>
- Palmer Dabbelt <palmer@sifive.com>
allOf:
- $ref: "spi-controller.yaml#"
properties:
compatible:
items:
- const: sifive,fu540-c000-spi
- const: sifive,spi0
description:
Should be "sifive,<chip>-spi" and "sifive,spi<version>".
Supported compatible strings are -
"sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated
onto the SiFive FU540 chip, and "sifive,spi0" for the SiFive
SPI v0 IP block with no chip integration tweaks.
Please refer to sifive-blocks-ip-versioning.txt for details
SPI RTL that corresponds to the IP block version numbers can be found here -
https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi
reg:
minItems: 1
items:
- description: SPI registers region
- description: Memory mapped flash region
interrupts:
maxItems: 1
clocks:
maxItems: 1
description:
Must reference the frequency given to the controller
sifive,fifo-depth:
description:
Depth of hardware queues; defaults to 8
$ref: "/schemas/types.yaml#/definitions/uint32"
enum: [8]
default: 8
sifive,max-bits-per-word:
description:
Maximum bits per word; defaults to 8
$ref: "/schemas/types.yaml#/definitions/uint32"
enum: [0, 1, 2, 3, 4, 5, 6, 7, 8]
default: 8
required:
- compatible
- reg
- interrupts
- clocks
unevaluatedProperties: false
examples:
- |
spi: spi@10040000 {
compatible = "sifive,fu540-c000-spi", "sifive,spi0";
reg = <0x10040000 0x1000>, <0x20000000 0x10000000>;
interrupt-parent = <&plic>;
interrupts = <51>;
clocks = <&tlclk>;
#address-cells = <1>;
#size-cells = <0>;
sifive,fifo-depth = <8>;
sifive,max-bits-per-word = <8>;
};
...
|
