| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2018-01-16 | soc: xilinx: xlnx_vcu: Use bitwise & rather than logical && on clkoutdiv | Gustavo A. R. Silva | |
| Currently clkoutdiv is being operated on by a logical && operator rather than a bitwise & operator. This looks incorrect as these should be bit flag operations. Addresses-Coverity-ID: 1463959 ("Logical vs. bitwise operator") Fixes: cee8113a295a ("soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver") Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com> Acked-by: Dhaval Shah <dshah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | |||
| 2018-01-08 | soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver | Dhaval Shah | |
| Xilinx ZYNQMP logicoreIP Init driver is based on the new LogiCoreIP design created. This driver provides the processing system and programmable logic isolation. Set the frequency based on the clock information get from the logicoreIP register set. Signed-off-by: Dhaval Shah <dshah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | |||
 |
index : linux.git | |
| Unnamed repository; edit this file 'description' to name the repository. |
| summaryrefslogtreecommitdiff |