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path: root/drivers/soc/imx/gpcv2.c
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2021-06-12soc: imx: gpcv2: add support for i.MX8MN power domainsAdam Ford
This adds support for the power domains founds on i.MX8MN. The Nano has fewer domains than the Mini, and the access to some of these domains is different than that of the Mini, the Mini power domains cannot be reused. Signed-off-by: Adam Ford <aford173@gmail.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-05-27soc: imx: gpcv2: move reset assert after requesting domain power upPeng Fan
The i.MX8MM VPU power up sequence is a bit special, it must follow: 1. request power up 2. reset assert 3. reset deassert This change in this patch will not affect other domains, because the power domain default is in asserted state, unless bootloader deassert the reset. It also applies to GPU power domain. Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-05-27soc: imx: gpcv2: Add support for missing i.MX8MM VPU/DISPMIX power domainsLucas Stach
With the BLK-CTL driver now in place, let's add the missing domains. Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-05-27soc: imx: gpcv2: add support for i.MX8MM power domainsLucas Stach
This adds support for the power domains found on i.MX8MM. The 2D and 3D GPU domains are abstracted as a single domain in the driver, as they can't be powered up/down individually due to a shared reset. Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-05-23soc: imx: gpcv2: add support for optional resetsLucas Stach
Normally the reset for the devices inside the power domain is triggered automatically from the PGC in the power-up sequencing, however on i.MX8MM this doesn't work for the GPU power domains. Add support for triggering the reset explicitly during the power up sequencing. Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-05-23soc: imx: gpcv2: allow domains without power-sequence controlLucas Stach
Some of the PGC domains only control the handshake with the ADB400 and don't have any power sequence controls. Make such domains work by allowing the pxx and map bits to be empty and skip all actions using those controls. Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-05-23soc: imx: gpcv2: add runtime PM support for power-domainsLucas Stach
This allows to nest domains into other power domains and have the parent domain powered up/down as required by the child domains. Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-05-23soc: imx: gpcv2: wait for ADB400 handshakeLucas Stach
New reference manuals show that there is actually a status bit for the ADB400 handshake. Add a poll loop to wait for the ADB400 to acknowledge our request. [Peng Fan: i.MX8MM has blk ctl module, the handshake can only finish after setting blk ctl. The blk ctl driver will set the bus clk bit and the handshake will finish there. we just add a delay and suppose the handshake will finish after that.] Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-05-23soc: imx: gpcv2: split power up and power down sequence controlLucas Stach
The current mixed function to control both power up and power down sequences is very hard to follow and already contains some sequence errors like triggering the ADB400 handshake at the wrong time due to this. Split the function into two, which results in slightly more code, but is way easier to get right. Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-05-23soc: imx: gpcv2: switch to clk_bulk_* APILucas Stach
Use clk_bulk API to simplify the code a bit. Also add some error checking to the clk_prepare_enable calls. Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-05-23soc: imx: gpcv2: move domain mapping to domain driver probeLucas Stach
As long as the power domain driver is active we want power control over the domain (which is what the mapping bit requests), so there is no point in whacking it for every power control action, simply set the bit in driver probe and clear it when the driver is removed. Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-05-23soc: imx: gpcv2: move to more ideomatic error handling in probeLucas Stach
Switch to "goto out..." error handling in domain driver probe to avoid repeating all the error paths. Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Adam Ford <aford173@gmail.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-08-22soc: imx: gpcv2: Use dev_err_probe() to simplify error handlingAnson Huang
dev_err_probe() can reduce code size, uniform error handling and record the defer probe reason etc., use it to simplify the code. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Guido Günther <agx@sigxcpu.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-14soc: imx: gpcv2: include linux/sizes.hLeonard Crestez
This header is included indirectly on arm/arm64 but not on x86 so CONFIG_COMPILE_TEST breaks. Fix by including <linux/sizes.h> directly. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-24soc: imx: gpcv2: Print the correct error codeGuido Günther
The current code prints 'ret' (thus 0) while it should use 'err'. Signed-off-by: Guido Günther <agx@sigxcpu.org> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11soc: imx: gpcv2: use devm_platform_ioremap_resource() to simplify codeAnson Huang
Use the new helper devm_platform_ioremap_resource() which wraps the platform_get_resource() and devm_ioremap_resource() together, to simplify the code. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Mukesh Ojha <mojha@codeaurora.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-03-19soc: imx: gpcv2: Make use of regmap_read_poll_timeout()Andrey Smirnov
Replace explicit polling loop with a call to regmap_read_poll_timeout() to avoid code repetition. Also fix misspelled "failed" while at it. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Chris Healy <cphealy@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-01-11soc: imx: gpcv2: handle reset clocksLucas Stach
Some power domains handled by the GPCv2 driver need to enable the clocks for devies inside the domain, so that the reset propagation and proper power-up sequencing happens. Handle them in the same way as on GPCv1. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-01-11soc: imx: gpcv2: handle additional power-down bits in handshake registerLucas Stach
Some of the i.MX8MQ domains have an additional control bit in the PU handshake (HSK) register. Documentation about this bit is a bit sparse at the moment, but it seems that it controls a power-down request to the AMBA domain bridge (ADB-400) attached to those domains. As the documentation doesn't desribe the usage of this bit yet, handle it in the same way as done in the ATF implementation. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-05soc: imx: gpcv2: add support for i.MX8MQ SoCLucas Stach
The GPCv2 on the Freescale i.MX8MQ SoC works in the same way as the GPCv2 on the i.MX7, but only controls more power domains with a different mapping. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-05soc: imx: gpcv2: move register access table to domain dataLucas Stach
The valid register ranges are defined by the implemented power domains, which are different between the individual SoCs where the GPCv2 is used. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-05soc: imx: gpcv2: prefix i.MX7 specific definesLucas Stach
So we can add i.MX8M support without introducing name clashes. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-10-01soc: imx: gpcv2: Switch to SPDX identifierFabio Estevam
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-10-01soc: imx: gpcv2: make pgc driver more generic for other i.MX platformsAnson Huang
i.MX8MQ and i.MX8MM share same gpc module with i.MX7D, they can reuse gpcv2 pgc driver for power domain control, this patch renames all functions and structure definitions started with "imx7" to "imx", and use .data in imx_gpcv2_dt_ids[] to pass platform specific power domain data for power domain driver, thus make gpcv2 pgc driver more generic for i.MX platforms. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-10-01soc: imx: gpcv2: use A_CORE instread of A7 for more i.MX platformsAnson Huang
gpcv2 driver is NOT just used on i.MX7D which has Cortex-A7 cores, but also on i.MX8MQ/i.MX8MM platforms which use Cortex-A53 cores, so let's use A_CORE instread of A7 to avoid confusion. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-06-17soc: imx: gpcv2: correct PGC offsetAnson Huang
Correct MIPI/PCIe/USB_HSIC's PGC offset based on design RTL, the values in the Reference Manual (Rev. 1, 01/2018 and the older ones) are incorrect. The correct offset values should be as below: 0x800 ~ 0x83F: PGC for core0 of A7 platform; 0x840 ~ 0x87F: PGC for core1 of A7 platform; 0x880 ~ 0x8BF: PGC for SCU of A7 platform; 0xA00 ~ 0xA3F: PGC for fastmix/megamix; 0xC00 ~ 0xC3F: PGC for MIPI PHY; 0xC40 ~ 0xC7F: PGC for PCIe_PHY; 0xC80 ~ 0xCBF: PGC for USB OTG1 PHY; 0xCC0 ~ 0xCFF: PGC for USB OTG2 PHY; 0xD00 ~ 0xD3F: PGC for USB HSIC PHY; Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Fixes: 03aa12629fc4 ("soc: imx: Add GPCv2 power gating driver") Acked-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-04-23soc: imx: gpcv2: Do not pass static memory as platform dataAndrey Smirnov
Platform device core assumes the ownership of dev.platform_data as well as that it is dynamically allocated and it will try to kfree it as a part of platform_device_release(). Change the code to use platform_device_add_data() n instead of a pointer to a static memory to avoid causing a BUG() when calling platform_device_put(). The problem can be reproduced by artificially enabling the error path of platform_device_add() call (around line 357). Note that this change also allows us to constify imx7_pgc_domains, since we no longer need to be able to modify it. Cc: Stefan Agner <stefan@agner.ch> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-08-05soc: imx: gpcv2: fix regulator deferred probeStefan Agner
If a regulator requests a deferred probe, the power domain gets initialized twice. This leads to a list double add (without list debugging the kernel hangs due to the double add later): WARNING: CPU: 0 PID: 19 at lib/list_debug.c:31 __list_add_valid+0xbc/0xc4 list_add double add: new=c1229754, prev=c12383b4, next=c1229754. Initialize the power domain after we get the regulator. Also do not print an error in case the regulator defers probing. Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Fixes: 03aa12629fc4 ("soc: imx: Add GPCv2 power gating driver") Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Andrey Smirnov <andrew.smirnov@gmail.com> Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-04-07soc: imx: Add GPCv2 power gating driverAndrey Smirnov
Add code allowing for control of various power domains managed by GPCv2 IP block found in i.MX7 series of SoCs. Power domains covered by this patch are: - PCIE PHY - MIPI PHY - USB HSIC PHY - USB OTG1/2 PHY Support for any other power domain controlled by GPC is not present, and can be added at some later point. Testing of this code was done against a PCIe driver. Cc: yurovsky@gmail.com Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Dong Aisheng <dongas86@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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