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path: root/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
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2020-09-15pinctrl: Rename sh-pfc to renesasGeert Uytterhoeven
The drivers/pinctrl/sh-pfc subdirectory was originally created to group pin control drivers for various Renesas SuperH and SH-Mobile platforms. However, the name "sh-pfc" no longer reflects its contents, as the directory now contains pin control drivers for Renesas SuperH, ARM32, and ARM64 SoCs. Hence rename the subdirectory from drivers/pinctrl/sh-pfc to drivers/pinctrl/renesas, and the related Kconfig symbol from PINCTRL_SH_PFC to PINCTRL_RENESAS. Rename the git branch in MAINTAINERS, too, for consistency. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200909131534.12897-3-geert+renesas@glider.be
2020-08-31pinctrl: sh-pfc: r8a7790: Add CAN pins, groups and functionsLad Prabhakar
Add pins, groups and functions for the CAN{0,1} interface. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> Link: https://lore.kernel.org/r/20200825095448.13093-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-08-17pinctrl: sh-pfc: r8a7790: Add USB1 PWEN pin and groupLad Prabhakar
Add USB1 PWEN pin and group for USB1 interface. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/1595005225-11519-2-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-05-15pinctrl: sh-pfc: r8a7790: Add r8a7742 PFC supportLad Prabhakar
Renesas RZ/G1H (R8A7742) is pin compatible with R-Car H2 (R8A7790), however it doesn't have several automotive specific peripherals. Add automotive-specific pin groups/functions along with common pin groups/functions for supporting both r8a7790 and r8a7742 SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1588542414-14826-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-06-04pinctrl: sh-pfc: r8a7790: Use new macros for non-GPIO pinsGeert Uytterhoeven
Update the R-Car H2 pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car H2 SoC (in 31x31 FCBGA package) by symbolic enum values, referring to signal names. Note that the user-visible names of these pins are still based on pin numbers instead of signal names, to preserve DT backwards compatibility. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-05-21pinctrl: sh-pfc: Rename 2-parameter CPU_ALL_PORT() variantGeert Uytterhoeven
There are two variants of the CPU_ALL_PORT() macro in use: 1. A three-parameter variant, to be provided for SoCs with a linear GPIO pin space ("PORT style"), 2. A two-parameter variant, to be provided for SoCs with 32-port GPIO banks ("GP port style"). Rename the 2-parameter variant to CPU_ALL_GP(), to avoid confusion, and to increase naming consistency. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-02pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macroGeert Uytterhoeven
Currently the PINMUX_CFG_REG_VAR() macro must be followed by initialization data, specifying all enum IDs. Hence the macro itself does not know anything about the enum IDs, preventing the macro from performing any validation on it. Make the macro accept the enum IDs as a parameter, and update all users. Note that array data enclosed by curly braces cannot be passed to a macro as a parameter, hence both the register field widths and the enum IDs are wrapped using the GROUP() macro. No functional changes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-04-02pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macroGeert Uytterhoeven
Currently the PINMUX_CFG_REG() macro must be followed by initialization data, specifying all enum IDs. Hence the macro itself does not know anything about the enum IDs, preventing the macro from performing any validation on it. Make the macro accept the enum IDs as a parameter, and update all users. Note that array data enclosed by curly braces cannot be passed to a macro as a parameter, hence the enum IDs are wrapped using a new macro GROUPS(). No functional changes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-04-02pinctrl: sh-pfc: Add missing #include <linux/errno.h>Geert Uytterhoeven
Source files using -Exxx error codes should include <linux/errno.h>. On ARM, this header file is included indirectly; on SuperH, it is not, leading to "error: ‘EINVAL’ undeclared" failures when enabling compile-testing later. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-01-21pinctrl: sh-pfc: r8a7790: Initialize TDSEL register for ES1.0Wolfram Sang
Documentation for ES1.0 says that some bits in TDSEL must be set (ch 5.3.39 in R-Car H2 v0.91). However, the reset value of the register is 0, so software has to do it. Add this to the kernel driver to ensure this is really done independent of firmware versions and use whitelisting for ES versions known to need this. This is needed for some SD cards supporting SDR104 transfer mode. For me, TDSEL was not initialized by the firmware and I had problems with the card when re-inserting it. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-11pinctrl: sh-pfc: Convert to SPDX identifiersKuninori Morimoto
This patch updates license to use SPDX-License-Identifier instead of verbose license text. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-03-21pinctrl: sh-pfc: r8a7790: Add missing TX_ER pin to avb_mii groupGeert Uytterhoeven
The pin controller drivers for all R-Car Gen2 SoCs have entries for the EtherAVB TX_ER pins in their EtherAVB MII groups, except on R-Car H2. Add the missing pin to restore consistency. Note that technically TX_ER is an optional signal in the MII bus, and thus could have its own group, but this is currently not supported by any R-Car Gen2 pin controller driver. Fixes: 19ef697d1eb7be06 ("sh-pfc: r8a7790: add EtherAVB pin groups") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2016-06-21pinctrl: sh-pfc: Improve core and user API separationGeert Uytterhoeven
The Renesas Pin Function Controller uses two header files: - sh_pfc.h, for use by both core code and SoC-specific drivers, - core.h, for internal use by the core code only. Several SoC-specific drivers include core.h, as they need the sh_pfc structure, which is passed explicitly to the various SoC-specific callbacks, and used there. Hence move its definition from core.h to sh_pfc.h, and remove the inclusion of core.h from all SoC-specific files. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-10pinctrl: sh-pfc: refactor voltage settingWolfram Sang
All known hardware being able to switch voltages has the same POCCTRL register. So, factor out the common code to the core and keep only the pin-to-bit mapping SoC specific. Convert the only user, r8a7790. In case POCCTRL should ever get more complex (more voltages to select?), we should probably switch over to a describing array like drive strength does currently. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-03-29pinctrl: sh-pfc: r8a7790: Implement voltage switching for SDHIWolfram Sang
All the SHDIs can operate with either 3.3V or 1.8V signals, depending on negotiation with the card. Implement the {get,set}_io_voltage operations and set the related capability flag for the associated pins. Signed-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Cc: linux-gpio@vger.kernel.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-02-08pinctrl: sh-pfc: Rename PINMUX_IPSR_DATA() to PINMUX_IPSR_GPSR()Geert Uytterhoeven
This macro describes a pinmux configuration that needs configuration in both a Peripheral Function Select Register (IPSR) and in a GPIO/Peripheral Function Select Register 1 (GPSR). Reflect that in the macro name for clarity. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2015-12-16pinctrl: sh-pfc: r8a7790: Add SCIF_CLK supportGeert Uytterhoeven
Add pins, groups, and a function for SCIF_CLK, which is the external clock source for the Baud Rate Generator for External Clock (BRG) on (H)SCIF. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2015-11-30pinctrl: sh-pfc: Share/reuse same PORT_GP_x() macrosKuninori Morimoto
Many SoC needs each PORT_GP_x() macros, but we can share/reuse same one. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-11-30pinctrl: sh-pfc: r8a7790: Use PINMUX_SINGLE() instead of raw PINMUX_DATA()Geert Uytterhoeven
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2015-10-20pinctrl: sh-pfc: Stop including <linux/platform_data/gpio-rcar.h>Geert Uytterhoeven
This header file will be removed soon. Copy the helper macro RCAR_GP_PIN(), which is used by the pinctrl drivers only, to sh_pfc.h, and drop the #include. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-20pinctrl: sh-pfc: Rename .gpio_data[] to .pinmux_data[]Geert Uytterhoeven
The sh_pfc_soc_info.gpio_data[] array contains not only GPIO data, but also various other pinmux-related data (functions and marks). Every single driver already calls its local array pinmux_data[]. Hence rename the sh_pfc_soc_info member to "pinmux_data". Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2015-10-20pinctrl: sh-pfc: r8a779[01]: Move 'union vin_data' to shared header fileSergei Shtylyov
R8A7790/1 PFC drivers use almost identical 'union vin_data' and completely identical VIN_DATA_PIN_GROUP() macro; we thus can move them into the shared header file... Suggested-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-10-02pinctrl: sh-pfc: r8a7790: use PINMUX_IPSR_MSEL()Kuninori Morimoto
Now, PINMUX_IPSR_MSEL() and PINMUX_IPSR_MODSEL_DATA() are same. Current PFC driver is very difficult to read, because macro names are using different length. PINMUX_IPSR_NOGP(ispr, ...) PINMUX_IPSR_DATA(ipsr, ...) PINMUX_IPSR_NOGM(ispr, ...) PINMUX_IPSR_NOFN(ipsr, ...) PINMUX_IPSR_MSEL(ipsr, ...) PINMUX_IPSR_MODSEL_DATA(ipsr, ...) It can be readable if we can use PINMUX_IPSR_MSEL() instead of PINMUX_IPSR_MODSEL_DATA() PINMUX_IPSR_NOGP(ispr, ...) PINMUX_IPSR_DATA(ipsr, ...) PINMUX_IPSR_NOGM(ispr, ...) PINMUX_IPSR_NOFN(ipsr, ...) PINMUX_IPSR_MSEL(ipsr, ...) Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-07-16sh-pfc: r8a7790: remove non-existing GPIO pinsLaurent Pinchart
GPIO banks 1 and 2 are missing pins 30 and 31. Remove them. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-19pinctrl: sh-pfc: r8a7790: Add PWM pin groups and functionsYoshihiro Shimoda
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-07sh-pfc: r8a7790: add EtherAVB pin groupsSergei Shtylyov
Add EtherAVB pin groups to R8A7790 PFC driver. Based on original patch by Mitsuhiro Kimura <mitsuhiro.kimura.kc@renesas.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-15sh-pfc: r8a7790: add MLB+ pin groupSergei Shtylyov
Add MLB+ 3-pin mode pin group to R8A7790 PFC driver. Based on original patch by Andrey Gusakov <andrey.gusakov@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-06-03Merge tag 'pinctrl-v3.16-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl into next Pull pin control changes from Linus Walleij: "This is the bulk of pin control changes for the v3.16 development cycle: - Antoine Tenart made the get_group_pins() vtable entry optional. - Antoine also provides an entirely new driver for the Marvell Berlin SoC. This is unrelated to the existing MVEBU hardware driver and warrants its own separate driver. - reflected from the GPIO subsystem there is a number of refactorings to make pin control drivers with gpiochips use the new gpiolib irqchip helpers. The following drivers were converted to use the new infrastructure: * ST Microelectronics STiH416 and friends * The Atmel AT91 * The CSR SiRF (Prima2) * The Qualcomm MSM series - massive improvements in the Qualcomm MSM driver from Bjorn Andersson, Andy Gross and Kumar Gala. Among those new support for the IPQ8064 and MSM8x74 SoC variants. - support for the Freescale i.MX6 SoloX SoC variant. - massive improvements in the Allwinner sunxi driver from Boris Brezillon, Maxime Ripard and Chen-Yu Tsai. - Renesas PFC updates from Laurent Pinchart, Kuninori Morimoto, Wolfram Sang and Magnus Damm. - Cleanups and refactorings of the nVidia Tegra driver from Stepgen Warren. - the Exynos driver now supports the Exynos3250 SoC. - Intel BayTrail updates from Jin Yao, Mika Westerberg. - the MVEBU driver now supports the Orion5x SoC variants, which is part of the effort of getting rid of the old Marvell kludges in arch/arm/mach-orion5x - Rockchip driver updates from Heiko Stuebner. - a ton of cleanups and janitorial patches from Axel Lin. - some minor fixes and improvements here and there" * tag 'pinctrl-v3.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (93 commits) pinctrl: sirf: fix a bad conflict resolution pinctrl: msm: Add more MSM8X74 pin definitions pinctrl: qcom: ipq8064: Fix naming convention pinctrl: msm: Add missing sdc1 and sdc3 groups pinctrl: sirf: switch to using allocated state container pinctrl: Enable "power-source" to be extracted from DT files pinctrl: sunxi: create irq/pin mapping during init pinctrl: pinconf-generic: Use kmemdup instead of kmalloc + memcpy pinctrl: berlin: Use devm_ioremap_resource() pinctrl: sirf: fix typo for GPIO bank number pinctrl: sunxi: depend on RESET_CONTROLLER pinctrl: sunxi: fix pin numbers passed to register offset helpers pinctrl: add pinctrl driver for imx6sx pinctrl/at91: Fix lockup when IRQ on PIOC and PIOD occurs pinctrl: msm: switch to using generic GPIO irqchip helpers pinctrl: sunxi: Fix multiple registration issue pinctrl: sunxi: Fix recursive dependency pinctrl: berlin: add the BG2CD pinctrl driver pinctrl: berlin: add the BG2 pinctrl driver pinctrl: berlin: add the BG2Q pinctrl driver ...
2014-04-23sh-pfc: r8a7790: Fix definition of IPSR5Guido Piasenza
The extra entry in the table makes SCIFA0_B, and all peripherals after it, fail. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: pfc: r8a7790: add mux data for IIC(B) coresWolfram Sang
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: pfc: r8a7790: add i2c0 muxingWolfram Sang
Add the muxing for the last missing i2c rcar core. Fix the sorting for SH_PFC_PIN_NAMED while we are here. Signed-off-by: Wolfram Sang <wsa@sang-engineering.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-05pinctrl: sh-pfc: r8a7790: Add alternative MSIOF pin groupsGeert Uytterhoeven
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25pinctrl: sh-pfc: r8a7790: Add QSPI pin groupsGeert Uytterhoeven
A QSPI function set consists of 3 groups: - qspi_ctrl (2 control wires) - qspi_data2 (2 data wires, for Single/Dual SPI) - qspi_data4 (4 data wires, for Quad SPI) Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-11pinctrl: sh-pfc: r8a7790: Break out USB0 OVC/VBUSMagnus Damm
Create a new group for the USB0 OVC/VBUS pin by itself. This allows us to monitor PWEN as GPIO on the Lager board. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-07pinctrl: sh-pfc: r8a7790: Fix vsync value in the vin3_sync_mux arrayValentine Barshak
This fixes a typo in the vin3_sync_mux array (s/VI2/VI3/). Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-20pinctrl: sh-pfc: ARM: Constify pins and cfg_regs arraysLaurent Pinchart
The arrays are never modified, declare them as const. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-10pinctrl: sh-pfc: pfc-r8a7790: Add VIN2 and VIN3 pinsValentine Barshak
There are VIN2 and VIN3 channels available on the R8A7790 SoC. VIN2 supports 4/8/16/18/24-bit data, while VIN3 supports 8-bit. Add both here, covering all possible data pin configurations. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2013-12-10pinctrl: sh-pfc: pfc-r8a7790: Add missing VIN1 pinsValentine Barshak
Both VIN0 and VIN1 channels support identical input interfaces. Add missing VIN1 pins here and organize them in the same pin groups as VIN0. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2013-12-10pinctrl: sh-pfc: pfc-r8a7790: Reorganize VIN0 data pinsValentine Barshak
This reorganizes and renames VIN0 data pin groups to cover all possible configurations. There's total of eight data pin groups, one per each configuration. Most of the groups share the same pin/mux array. Only the 18-bit configuration needs a separate pin/mux array since in combines interleaved data pins. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2013-12-10pinctrl: sh-pfc: pfc-r8a7790: Group VIN0 HSYNC and VSYNC togetherValentine Barshak
This groups VIN0 HSYNC and VSYNC pins together since one cannot be used without another. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2013-12-10pinctrl: sh-pfc: pfc-r8a7790: Rename VIN pin groupsValentine Barshak
This drops superfluous "signal" word from the pin group names and renames data_enable group to clkenb as in the h/w manual. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2013-12-10sh-pfc: r8a7790: Add Audio pin supportKuninori Morimoto
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-12-10sh-pfc: r8a7790: Add SSI pin supportKuninori Morimoto
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-09-27sh-pfc: r8a7790: add pin definitions for the I2C3 interfaceGuennadi Liakhovetski
There are four I2C interfaces on r8a7790, each of them can be connected to one of the two respective I2C controllers, e.g. interface #0 can be configured to work with I2C0 or with IIC0. Additionally some of those interfaces can also use one of several pin sets. Interface #3 is special, because it can be used in automatic mode for DVFS. It only has one set of pins available and those pins cannot be used for anything else, they also lack the GPIO function. This patch uses the sh-pfc ability to configure pins, not associated with GPIOs and adds support for I2C3 to the r8a7790 PFC set up. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-09-24sh-pfc: r8a7790: Add I2C pin groups and functionsUlrich Hecht
Adds pinmux for i2c bus 1 and 2. (Pins for 0 and 3 are not multiplexed.) Signed-off-by: Ulrich Hecht <ulrich.hecht@gmail.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-08-14sh-pfc: r8a7790: Add DU pin groups and functionsLaurent Pinchart
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-14sh-pfc: r8a7790: Rename DU1_DOTCLKIN to DU_DOTCLKIN1Laurent Pinchart
Name the DU clock input 1 consistently with clock inputs 0 and 2. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-07-29Merge branch 'pinmux/next/fixes' of git://linuxtv.org/pinchartl/fbdev into develLinus Walleij
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-07-29sh-pfc: r8a7790: Add VIN pin groups and functionsShinobu Uehara
Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com> Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-07-29sh-pfc: r8a7790: Add USB pin groups and functionsShinobu Uehara
Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com> Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-22 23:32:53 +0000