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path: root/drivers/media
AgeCommit message (Expand)Author
2021-02-17v4l: ioctl: Use %p4cc printk modifier to print FourCC codesSakari Ailus
2020-12-16Merge tag 'arm-soc-drivers-5.11' of git://git.kernel.org/pub/scm/linux/kernel...Linus Torvalds
2020-12-15Merge tag 'pm-5.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafa...Linus Torvalds
2020-12-15Merge tag 'spi-v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/brooni...Linus Torvalds
2020-12-15Merge tag 'net-next-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/ne...Linus Torvalds
2020-12-14Merge tag 'media/v5.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mc...Linus Torvalds
2020-12-14Merge branch 'opp/linux-next' of git://git.kernel.org/pub/scm/linux/kernel/gi...Rafael J. Wysocki
2020-12-14Merge tag 'drm-next-2020-12-11' of git://anongit.freedesktop.org/drm/drmLinus Torvalds
2020-12-11Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski
2020-12-10Merge series "spi: spi-geni-qcom: Use gpio descriptors for CS" from Stephen B...Mark Brown
2020-12-09media: venus: dev_pm_opp_put_*() accepts NULL argumentViresh Kumar
2020-12-08media: vidtv: fix some warningsMauro Carvalho Chehab
2020-12-07media: ccs: Add support for obtaining C-PHY configuration from firmwareSakari Ailus
2020-12-07media: ccs-pll: Print pixel ratesSakari Ailus
2020-12-07media: ccs: Print written register valuesSakari Ailus
2020-12-07media: ccs: Add support for DDR OP SYS and OP PIX clocksSakari Ailus
2020-12-07media: ccs-pll: Add support for DDR OP system and pixel clocksSakari Ailus
2020-12-07media: ccs: Dual PLL supportSakari Ailus
2020-12-07media: ccs-pll: Add trivial dual PLL supportSakari Ailus
2020-12-07media: ccs-pll: Separate VT divisor limit calculation from the restSakari Ailus
2020-12-07media: ccs-pll: Fix VT post-PLL divisor calculationSakari Ailus
2020-12-07media: ccs-pll: Make VT divisors 16-bitSakari Ailus
2020-12-07media: ccs-pll: Rework bounds checksSakari Ailus
2020-12-07media: ccs-pll: Print relevant information on PLL treeSakari Ailus
2020-12-07media: ccs-pll: Better separate OP and VT sub-tree calculationSakari Ailus
2020-12-07media: ccs-pll: Check for derating and overrating, support non-derating sensorsSakari Ailus
2020-12-07media: ccs-pll: Split off VT subtree calculationSakari Ailus
2020-12-07media: ccs-pll: Add C-PHY supportSakari Ailus
2020-12-07media: ccs-pll: Add sanity checksSakari Ailus
2020-12-07media: ccs-pll: Add support flexible OP PLL pixel clock dividerSakari Ailus
2020-12-07media: ccs-pll: Support two cycles per pixel on OP domainSakari Ailus
2020-12-07media: ccs-pll: Add support for extended input PLL clock dividerSakari Ailus
2020-12-07media: ccs-pll: Add support for decoupled OP domain calculationSakari Ailus
2020-12-07media: ccs: Add support for lane speed modelSakari Ailus
2020-12-07media: ccs-pll: Add support for lane speed modelSakari Ailus
2020-12-07media: ccs-pll: Use explicit 32-bit unsigned typeSakari Ailus
2020-12-07media: ccs-pll: Fix check for PLL multiplier upper boundSakari Ailus
2020-12-07media: ccs-pll: Fix comment on check against maximum PLL multiplierSakari Ailus
2020-12-07media: ccs-pll: Avoid overflow in pre-PLL divisor lower bound searchSakari Ailus
2020-12-07media: ccs-pll: Fix condition for pre-PLL divider lower boundSakari Ailus
2020-12-07media: ccs-pll: Begin calculation from OP system clock frequencySakari Ailus
2020-12-07media: ccs-pll: Use the BIT macroSakari Ailus
2020-12-07media: ccs-pll: Document the structs in the header as well as the functionSakari Ailus
2020-12-07media: ccs-pll: Move the flags field down, away from 8-bit fieldsSakari Ailus
2020-12-07media: ccs-pll: Differentiate between CSI-2 D-PHY and C-PHYSakari Ailus
2020-12-07media: ccs-pll: Remove parallel bus supportSakari Ailus
2020-12-07media: ccs-pll: End search if there are no better values availableSakari Ailus
2020-12-07media: ccs-pll: Use correct VT divisor for calculating VT SYS divisorSakari Ailus
2020-12-07media: ccs-pll: Split limits and PLL configuration into front and back partsSakari Ailus
2020-12-07media: ccs-pll: Don't use div_u64 to divide a 32-bit numberSakari Ailus
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