summaryrefslogtreecommitdiff
path: root/drivers/media/video/cx18/cx18-av-audio.c
AgeCommit message (Collapse)Author
2012-08-15[media] rename most media/video pci drivers to media/pciMauro Carvalho Chehab
Rename all PCI drivers with their own directory under drivers/media/video into drivers/media/pci and update the building system. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2011-03-21[media] cx18: Use the control frameworkHans Verkuil
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2010-06-01V4L/DVB: cx18, cx23885, v4l2 doc, MAINTAINERS: Update Andy Walls' email addressAndy Walls
A trivial change to update my email address from my dead awalls@radix.net address to my current awalls@md.metrocast.net address. Signed-off-by: Andy Walls <awalls@md.metrocast.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2009-03-30V4L/DVB (11310): cx18: remove intermediate 'ioctl' stepHans Verkuil
The audio and vbi parts still used an 'ioctl'-like interface. Replace this with normal functions. Cc: Andy Walls <awalls@radix.net> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2008-12-30V4L/DVB (9937): cx18: Use a consistent crystal value for computing all PLL ↵Andy Walls
parameters Use a consistent crystal value of 28.636360 MHz for computing all PLL parameters so clocks don't have relative error due to assumed crystal value mismatches. Also aimed to have all PLLs run their VOCs at close to 400 MHz to minimze the error of these PLLs as frequency synthesizers. Also set the VDCLK and AIMCLK PLLs to sane values before the APU and CPU firmware are loaded. Also fixed I2S Master clock dividers. Many thanks to Mike Bradley and Jeff Campbell for reporting this problem and suggesting the solution, researching and experimenting, and performing extensive testing to support their suggested solution. Reported-by: Jeff Campbell <jac1dlists@gmail.com> Reported-by: Mike Bradley <mike.bradley@incanetworks.com> Signed-off-by: Andy Walls <awalls@radix.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2008-12-30V4L/DVB (9936): cx18: Disable locking of Video and Audio PLL for analog capturesAndy Walls
Disable AV_LOCK, locking of audio PLL to video PLL in the cx18-av-core for analog captures. It seems to have adverse effects on captures from SVideo and CVBS sources with current clock & crystal settings in the driver. Many thanks to Jeff Campbell and Mike Bradley for reporting this problem, and suggesting the solution and performing extensive testing to support their suggestion. Reported-by: Jeff Campbell <jac1dlists@gmail.com> Reported-by: Mike Bradley <mike.bradley@incanetworks.com> Signed-off-by: Andy Walls <awalls@radix.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2008-12-30V4L/DVB (9728): cx18: Copyright attribution update for files modified by awallsAndy Walls
Add copyright attribution for files modified by awalls in 2008 Signed-off-by: Andy Walls <awalls@radix.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2008-12-29V4L/DVB (9512): cx18: Fix write retries for registers that always change - ↵Andy Walls
part 3. cx18: Fix write retries for registers that always change - part 3. Fix the io for the rest of the registers that will often not read back the value just written. Modified register readback checks to make sure the intended effect was achieved without constantly rewriting the registers. The one outstanding register remaining is 0xc72014 CX18_AUDIO_ENABLE, whose behavior on writes I have yet to determine. Signed-off-by: Andy Walls <awalls@radix.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2008-07-26V4L/DVB (8462): cx18: Lock the aux PLL to the video pixle rate for analog ↵Andy Walls
captures cx18: Lock the aux PLL to the video pixel rate for analog captures. The datasheet for the CX25840 says this is important for MPEG encoding applications. To ensure the PLL locking was correct, also fixed the aux PLL's multiplier to be computed based on a precise crystal freq of 4.5 MHz/286 * 455/2 * 8 = 28636363.6363... instead of the imporperly rounded 28636363. Signed-off-by: Andy Walls <awalls@radix.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
2008-07-26V4L/DVB (8461): cx18: Fix 32 kHz audio sample output rate for analog tuner ↵Andy Walls
SIF input cx18: Fix 32 kHz audio sample output rate for analog tuner SIF input so it works. The AUX_PLL VCO was being operated at 196.6 MHz out of the spec'ed 200-600 MHz range. Fixed the multipler and post dividers to operate the VCO within specification and added comments on how magic numbers are derived. Thanks to Hans Verkuil for pointing out this interesting problem to solve. Signed-off-by: Andy Walls <awalls@radix.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
2008-07-20V4L/DVB (8167): cx18: set correct audio inputs for tuner and line-in 2.Hans Verkuil
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
2008-04-29V4L/DVB (7786): cx18: new driver for the Conexant CX23418 MPEG encoder chipHans Verkuil
Many thanks to Steve Toth from Hauppauge and Nattu Dakshinamurthy from Conexant for their support. I am in particular thankful to Hauppauge since without their help this driver would not exist. It should also be noted that Steve did the work to get the DVB part up and running. Thank you! Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl> Signed-off-by: Steven Toth <stoth@hauppauge.com> Signed-off-by: Michael Krufky <mkrufky@linuxtv.org> Signed-off-by: G. Andrew Walls <awalls@radix.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>