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Age	Commit message (Expand)	Author
2020-12-07	media: ccs-pll: Add support for DDR OP system and pixel clocks	Sakari Ailus
2020-12-07	media: ccs-pll: Add trivial dual PLL support	Sakari Ailus
2020-12-07	media: ccs-pll: Rework bounds checks	Sakari Ailus
2020-12-07	media: ccs-pll: Check for derating and overrating, support non-derating sensors	Sakari Ailus
2020-12-07	media: ccs-pll: Add support flexible OP PLL pixel clock divider	Sakari Ailus
2020-12-07	media: ccs-pll: Support two cycles per pixel on OP domain	Sakari Ailus
2020-12-07	media: ccs-pll: Add support for extended input PLL clock divider	Sakari Ailus
2020-12-07	media: ccs-pll: Add support for decoupled OP domain calculation	Sakari Ailus
2020-12-07	media: ccs-pll: Add support for lane speed model	Sakari Ailus
2020-12-07	media: ccs-pll: Use the BIT macro	Sakari Ailus
2020-12-07	media: ccs-pll: Document the structs in the header as well as the function	Sakari Ailus
2020-12-07	media: ccs-pll: Move the flags field down, away from 8-bit fields	Sakari Ailus
2020-12-07	media: ccs-pll: Differentiate between CSI-2 D-PHY and C-PHY	Sakari Ailus
2020-12-07	media: ccs-pll: Remove parallel bus support	Sakari Ailus
2020-12-07	media: ccs-pll: Split limits and PLL configuration into front and back parts	Sakari Ailus
2020-12-03	media: ccs: Change my e-mail address	Sakari Ailus
2020-12-03	media: smiapp-pll: Rename as ccs-pll	Sakari Ailus