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ccs-pll.c
Age
Commit message (
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Author
2020-12-07
media: ccs-pll: Print pixel rates
Sakari Ailus
2020-12-07
media: ccs-pll: Add support for DDR OP system and pixel clocks
Sakari Ailus
2020-12-07
media: ccs: Dual PLL support
Sakari Ailus
2020-12-07
media: ccs-pll: Add trivial dual PLL support
Sakari Ailus
2020-12-07
media: ccs-pll: Separate VT divisor limit calculation from the rest
Sakari Ailus
2020-12-07
media: ccs-pll: Fix VT post-PLL divisor calculation
Sakari Ailus
2020-12-07
media: ccs-pll: Make VT divisors 16-bit
Sakari Ailus
2020-12-07
media: ccs-pll: Rework bounds checks
Sakari Ailus
2020-12-07
media: ccs-pll: Print relevant information on PLL tree
Sakari Ailus
2020-12-07
media: ccs-pll: Better separate OP and VT sub-tree calculation
Sakari Ailus
2020-12-07
media: ccs-pll: Check for derating and overrating, support non-derating sensors
Sakari Ailus
2020-12-07
media: ccs-pll: Split off VT subtree calculation
Sakari Ailus
2020-12-07
media: ccs-pll: Add C-PHY support
Sakari Ailus
2020-12-07
media: ccs-pll: Add sanity checks
Sakari Ailus
2020-12-07
media: ccs-pll: Add support flexible OP PLL pixel clock divider
Sakari Ailus
2020-12-07
media: ccs-pll: Support two cycles per pixel on OP domain
Sakari Ailus
2020-12-07
media: ccs-pll: Add support for extended input PLL clock divider
Sakari Ailus
2020-12-07
media: ccs-pll: Add support for decoupled OP domain calculation
Sakari Ailus
2020-12-07
media: ccs-pll: Add support for lane speed model
Sakari Ailus
2020-12-07
media: ccs-pll: Use explicit 32-bit unsigned type
Sakari Ailus
2020-12-07
media: ccs-pll: Fix check for PLL multiplier upper bound
Sakari Ailus
2020-12-07
media: ccs-pll: Fix comment on check against maximum PLL multiplier
Sakari Ailus
2020-12-07
media: ccs-pll: Avoid overflow in pre-PLL divisor lower bound search
Sakari Ailus
2020-12-07
media: ccs-pll: Fix condition for pre-PLL divider lower bound
Sakari Ailus
2020-12-07
media: ccs-pll: Begin calculation from OP system clock frequency
Sakari Ailus
2020-12-07
media: ccs-pll: Differentiate between CSI-2 D-PHY and C-PHY
Sakari Ailus
2020-12-07
media: ccs-pll: Remove parallel bus support
Sakari Ailus
2020-12-07
media: ccs-pll: End search if there are no better values available
Sakari Ailus
2020-12-07
media: ccs-pll: Use correct VT divisor for calculating VT SYS divisor
Sakari Ailus
2020-12-07
media: ccs-pll: Split limits and PLL configuration into front and back parts
Sakari Ailus
2020-12-07
media: ccs-pll: Don't use div_u64 to divide a 32-bit number
Sakari Ailus
2020-12-03
media: ccs: Change my e-mail address
Sakari Ailus
2020-12-03
media: ccs-pll: Fix MODULE_LICENSE
Sakari Ailus
2020-12-03
media: smiapp-pll: Rename as ccs-pll
Sakari Ailus