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path: root/drivers/mailbox/qcom-apcs-ipc-mailbox.c
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2021-06-26mailbox: qcom: Add MSM8939 APCS supportShawn Guo
Enable MSM8939 APCS support by adding the compatible. It reuses msm8916_apcs_data. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-06-26mailbox: qcom: Use PLATFORM_DEVID_AUTO to register platform deviceShawn Guo
In adding APCS clock support for MSM8939, the second clock registration fails due to duplicate device name like below. [ 0.519657] sysfs: cannot create duplicate filename '/bus/platform/devices/qcom-apcs-msm8916-clk' ... [ 0.661158] qcom_apcs_ipc b111000.mailbox: failed to register APCS clk This is because MSM8939 has 3 APCS instances for Cluster0 (little cores), Cluster1 (big cores) and CCI (Cache Coherent Interconnect). Although only APCS of Cluster0 and Cluster1 have IPC bits, each of 3 APCS has A53PLL clock control bits. That said, 3 'qcom-apcs-msm8916-clk' devices need to be registered to instantiate all 3 clocks. Use PLATFORM_DEVID_AUTO rather than PLATFORM_DEVID_NONE for platform_device_register_data() call to fix the issue above. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-06-26mailbox: qcom-apcs: Add SM6125 compatibleMartin Botka
This commit adds compatible for the SM6125 SoC Signed-off-by: Martin Botka <martin.botka@somainline.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-02-14mailbox: qcom: Add support for SDX55 APCS IPCManivannan Sadhasivam
In SDX55, the IPC bits are located in the APCS GCC block. Also, this block can provide clock functionality. Hence, add support for IPC with correct offset and name of the clock provider. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-02-14mailbox: qcom: Add SC8180X apcs compatibleBjorn Andersson
The Qualcomm SC8180X platform has a APSS block exposing the usual IPC bits, add a compatible for this. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-08-03mailbox: qcom: Add msm8994 apcs compatibleKonrad Dybcio
MSM8994 has an APCS block similar to 8916, but with a different clock driver due to the former one having 2 clusters. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-08-03mailbox: qcom: Add sdm660 hmss compatibleKonrad Dybcio
The Qualcomm SDM660 platform has a APCS HMSS GLOBAL block, add the compatible for this. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-06-10mailbox: qcom: Add ipq6018 apcs compatibleSivaprakash Murugesan
The Qualcomm ipq6018 has apcs block, add compatible for the same. Also, the ipq6018 apcs provides a clock functionality similar to msm8916 but the clock driver is different. Create a child device based on the apcs compatible for the clock controller functionality. Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-06-10mailbox: qcom: Add clock driver name in apcs mailbox driver dataSivaprakash Murugesan
Some apcs mailbox devices supports a clock driver, the compatible strings of devices supporting clock driver along with the clock driver name are maintained in a separate structure within the mailbox driver. And the clock driver is added based on device match. With increase in number of devices supporting the clock feature move the clock driver name inside the driver data. so that we can use a single API to get the register offset of mailbox driver and clock driver name together, and the clock driver will be added based on the driver data. Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-09-17mailbox: qcom-apcs: fix max_register valueJorge Ramirez-Ortiz
The mailbox length is 0x1000 hence the max_register value is 0xFFC. Fixes: c6a8b171ca8e ("mailbox: qcom: Convert APCS IPC driver to use regmap") Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-09-17mailbox: qcom: Add support for IPQ8074 APCSGokul Sriram Palanisamy
Add support of IPQ8074 with IPC register offset as 8. Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-09-17mailbox: qcom: Add support for Qualcomm SM8150 and SC7180 SoCsSibi Sankar
Add the corresponding APSS shared offset for SM8150 and SC7180 SoCs. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-09-17mbox: qcom: replace integer with valid macroJorge Ramirez-Ortiz
Use the correct macro when registering the platform device. Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-09-17mbox: qcom: add APCS child device for QCS404Jorge Ramirez-Ortiz
There is clock controller functionality in the APCS hardware block of qcs404 devices similar to msm8916. Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 284Thomas Gleixner
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 and only version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 294 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.825281744@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-12-21mailbox: qcom-apcs: Use device-managed registration APIThierry Reding
Get rid of some boilerplate driver removal code by using the newly added device-managed registration API. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2018-09-29mailbox: qcom: Add QCS404 APPS Global compatibleBjorn Andersson
Add support for the QCS404 APPS Global block with IPC register at offset 8. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2018-06-06mailbox: Add support for Qualcomm SDM845 SoCsSibi Sankar
Add the corresponding APSS shared offset for SDM845 SoC Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2018-06-06mailbox: qcom: Add msm8998 hmss compatibleBjorn Andersson
The Qualcomm MSM8998 platform has a APCS HMSS GLOBAL block, add the compatible for this. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2018-02-04mailbox: qcom: Create APCS child device for clock controllerGeorgi Djakov
There is a clock controller functionality provided by the APCS hardware block of msm8916 devices. The device-tree would represent an APCS node with both mailbox and clock provider properties. Create a platform child device for the clock controller functionality so the driver can probe and use APCS as parent. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2018-02-04mailbox: qcom: Convert APCS IPC driver to use regmapGeorgi Djakov
This hardware block provides more functionalities that just IPC. Convert it to regmap to allow other child platform devices to use the same regmap. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2017-06-14mailbox: Introduce Qualcomm APCS IPC driverBjorn Andersson
This implements a driver that exposes the IPC bits found in the APCS Global block in various Qualcomm platforms. The bits are used to signal inter-processor communication signals from the application CPU to other masters. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
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