| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-09-05 | irqchip/sifive-plic: set max threshold for ignored handlers | Christoph Hellwig |
| 2019-02-21 | irqchip/sifive-plic: Implement irq_set_affinity() for SMP host | Anup Patel |
| 2019-02-21 | irqchip/sifive-plic: Differentiate between PLIC handler and context | Anup Patel |
| 2019-02-21 | irqchip/sifive-plic: Add warning in plic_init() if handler already present | Anup Patel |
| 2019-02-21 | irqchip/sifive-plic: Pre-compute context hart base and enable base | Anup Patel |
| 2019-02-14 | irqchip/irq-sifive-plic: Check and continue in case of an invalid cpuid. | Atish Patra |
| 2018-10-22 | RISC-V: Use Linux logical CPU number instead of hartid | Atish Patra |
| 2018-10-22 | RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid | Palmer Dabbelt |
| 2018-08-13 | irqchip: add a SiFive PLIC driver | Christoph Hellwig |
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index : linux.git | |
| Unnamed repository; edit this file 'description' to name the repository. |
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