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path: root/drivers/gpu/drm
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2019-04-10drm/bochs: use simple display pipeGerd Hoffmann
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Noralf Trønnes <noralf@tronnes.org> Link: http://patchwork.freedesktop.org/patch/msgid/20190410074828.10296-1-kraxel@redhat.com
2019-04-10drm: switch drm_fb_xrgb8888_to_rgb888_dstclip to accept __iomem dstGerd Hoffmann
Not all archs have the __io_virt() macro, so cirrus can't simply convert pointers that way. The drm format helpers have to use memcpy_toio() instead. This patch makes drm_fb_xrgb8888_to_rgb888_dstclip() accept a __iomem dst pointer and use memcpy_toio() instead of memcpy(). The helper function (drm_fb_xrgb8888_to_rgb888_line) has been changed to process a single scanline. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Noralf Trønnes <noralf@tronnes.org> Link: http://patchwork.freedesktop.org/patch/msgid/20190410063815.17062-4-kraxel@redhat.com
2019-04-10drm: switch drm_fb_xrgb8888_to_rgb565_dstclip to accept __iomem dstGerd Hoffmann
Not all archs have the __io_virt() macro, so cirrus can't simply convert pointers that way. The drm format helpers have to use memcpy_toio() instead. This patch makes drm_fb_xrgb8888_to_rgb565_dstclip() accept a __iomem dst pointer and use memcpy_toio() instead of memcpy(). The helper function (drm_fb_xrgb8888_to_rgb565_line) has been changed to process a single scanline. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Noralf Trønnes <noralf@tronnes.org> Link: http://patchwork.freedesktop.org/patch/msgid/20190410063815.17062-3-kraxel@redhat.com
2019-04-10drm: switch drm_fb_memcpy_dstclip to accept __iomem dstGerd Hoffmann
Not all archs have the __io_virt() macro, so cirrus can't simply convert pointers that way. The drm format helpers have to use memcpy_toio() instead. This patch makes drm_fb_memcpy_dstclip() accept a __iomem dst pointer and use memcpy_toio() instead of memcpy(). With that separating out the memcpy loop into the drm_fb_memcpy_lines() helper isn't useful any more, so move the code back into the calling functins. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Noralf Trønnes <noralf@tronnes.org> Link: http://patchwork.freedesktop.org/patch/msgid/20190410063815.17062-2-kraxel@redhat.com
2019-04-10drm/amd/display: fix is odm head pipe logicDmytro Laktyushkin
Simply return true/false, don't iterate up the tree. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amd/display: Pass plane caps into amdgpu_dm_plane_initNicholas Kazlauskas
[Why] When deciding to add properties or expose formats on DRM planes we should be querying the caps for the DC plane it's supposed to represent. [How] Pass plane caps down into plane initialization, refactoring overlay plane initialization to have the overlay plane be represented by the first overlay capable DC plane. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amd/display: Clean up locking in dcn*_apply_ctx_for_surface()Leo Li
[Why] dcn*_disable_plane() doesn't unlock the pipe anymore, making the extra lock unnecessary. In addition - during full plane updates - all necessary pipes should be locked/unlocked together when modifying hubp to avoid tearing in pipesplit setups. [How] Remove redundant locks, and add function to lock all pipes. If an interdependent pipe update is required, lock down all pipes. Otherwise, lock only the top pipe for the updated pipe tree. Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amd/display: Recreate private_obj->state during S3 resumeLeo Li
[Why] When entering S3, amdgpu first calls DRM to cache the current atomic state, then commit the 'all-disabled' state. This sets dc->current_state to point at the private atomic object's dm_atomic_state->context, as any regular atomic commit would. Afterwards, amdgpu_dm calls dc_set_power_state() with S3 power state. This invalidates dc->current_state by wiping it to 0, consequently wiping dm_atomic_state->context. During resume, the cached atomic state is restored. When getting the private object however, the dm_atomic_state - containing the wiped context - is duplicated into the atomic state. This causes DC validation to fail during atomic check, as necessary function pointers in dc_state are now NULL. [How] Recreate the private object's dm_atomic_state->context during resume, restoring any static values such as function pointers. A TODO item is added to move static read-only values out of dc_state - they shouldn't be there anyways. Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amd/display: HDR visual confirmation incorrectly reports black colorMurton Liu
[Why] Checking against a TF that is unused causes us to default to black [How] Check against PQ instead Signed-off-by: Murton Liu <murton.liu@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amd/display: fix underflow on bootEric Yang
[Why] New seamless boot sequence introduced a bug where front end is disabled without blanking otg. [How] Adjust the condition of blanking otg to match seamless boot. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amd/display: disable link before changing link settingsAnthony Koo
[Why] If link is already enabled at a different rate (for example 5.4 Gbps) then calling VBIOS command table to switch to a new rate (for example 2.7 Gbps) will not take effect. This can lead to link training failure to occur. [How] If the requested link rate is different than the current link rate, the link must be disabled in order to re-enable at the new link rate. In today's logic it is currently only impacting eDP since DP connection types will always disable the link during display detection, when initial link verification occurs. Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amd/display: init dc_config before rest of DC initAnthony Koo
[Why] In some cases we want DC init to take in some config options [How] Init dc_config before rest of DC init Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amd/display: Call hwss.set_cursor_sdr_white_level, if availableSivapiriyanKumarasamy
[Why] In HDR configurations, the cursor - in SDR - needs to have it's white level boosted. [How] Program the cursor boost in update_dchubp_dpp like the other cursor attributes. Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Reza Amini <Reza.Amini@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amd/display: Set surface color space from DRM plane stateNicholas Kazlauskas
[Why] We need DC's color space to match the color encoding and color space specified by userspace to correctly render YUV surfaces. [How] Convert the DRM color encoding and color range properties to the appropriate DC colorspace option and update the color space when performing surface updates. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amd/display: prefer preferred link cap over verified link settingsWenjing Liu
[why] when preferred link cap is set, we should always use preferred in all validation. we should not use preferred for some validation but use verified for others. [how] create getter function that gets verified link cap. if preferred is set, return preferred link settings instead. Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amd/display: remove min reduction for abm 2.2 level 3Josip Pavic
[Why] Image brightness compensation for solid color full screen images is expected to be optimal for ABM 2.2 at level 3. The min reduction that is currently being enforced prevents this from being achieved. [How] Remove the min reduction for ABM 2.2 at level 3 Signed-off-by: Josip Pavic <Josip.Pavic@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amd/display: 3.2.25Aric Cyr
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amd/display: return correct dc_status for dcn10_validate_globalSu Sung Chung
[Why] Before it was returning false in the case of failure even though return type should be enum dc_status [How] Return DC_FAIL_UNSUPPORTED_1 instead Signed-off-by: Su Sung Chung <Su.Chung@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amd/display: Use plane->color_space for dpp if specifiedNicholas Kazlauskas
[Why] The input color space for the plane was previously ignored even if it was set. If a limited range YUV format was given to DC then the wrong color transformation matrix was being used since DC assumed that it was full range instead. [How] Respect the given color_space format for the plane if it isn't COLOR_SPACE_UNKNOWN. Otherwise, use the implicit default since DM didn't specify. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com> Acked-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amd/display: Calculate link bandwidth in a common functionNikola Cornij
[why] Currently link bandwidth is calculated in two places, using the same formula. They should be unified into calling one function. [how] Replace all implementations of link bandwidth calculation with a call to a function. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amd/display: fix clk_mgr namingDmytro Laktyushkin
clk_mgr is called dccg in dc_state, this change fixes that Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amd/display: use proper formula to calculate bandwidth from timingWenjing Liu
[why] The existing calculation uses a wrong formula to calculate bandwidth from timing. [how] Expose the existing proper function that calculates the bandwidth, so dc_link can use it to calculate timing bandwidth correctly. Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amd/display: fix dp_hdmi_max_pixel_clk unitsSivapiriyanKumarasamy
[Why] We are incorrectly using dp_hdmi_max_pixel_clk because the units are not clear. [How] Rename to dp_hdmi_max_pixel_clk_in_khz, and change mode timing validation to use the value correctly. Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amd/display: Add debugfs entry for amdgpu_dm_visual_confirmNicholas Kazlauskas
[Why] DC provides a few visual confirmation debug options that can be dynamically changed at runtime to help debug surface programming issues but we don't have any way to access it from userspace. [How] Add the amdgpu_dm_visual_confirm debugfs entry. It accepts a string containing the DC visual confirm enum value using the debugfs attribute helpers. The debugfs_create_file_unsafe can be used instead of debugfs_create_file as per the documentation. v2: Use debugfs helpers for getting and setting the value (Christian) Cc: Leo Li <sunpeng.li@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amd/display: Initialize stream_update with memsetNicholas Kazlauskas
The brace initialization used here generates warnings on some compilers. For example, on GCC 4.9: [...] In function ‘dm_determine_update_type_for_commit’: [...] error: missing braces around initializer [-Werror=missing-braces] struct dc_stream_update stream_update = { 0 }; ^ Use memset to make this more portable. v2: Specify the compiler / diagnostic in the commit message (Paul) Cc: Sun peng Li <Sunpeng.Li@amd.com> Cc: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amd/display: Remove semicolon from to_dm_plane_state definitionNicholas Kazlauskas
The extra ; in the macro definition creates an empty statement preventing any variable declarations from occuring after any use of to_dm_plane_state(...). Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amdgpu: support dpm level modification under virtualization v3Yintian Tao
Under vega10 virtualuzation, smu ip block will not be added. Therefore, we need add pp clk query and force dpm level function at amdgpu_virt_ops to support the feature. v2: add get_pp_clk existence check and use kzalloc to allocate buf v3: return -ENOMEM for allocation failure and correct the coding style Signed-off-by: Yintian Tao <yttao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amdgpu: Always enable memory sharing within same XGMI hiveshaoyunl
XGMI Memory sharing will be disbaled by default for security reason after boot up, it depends on driver to enable the memory sharing Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amdgpu: Add a check to avoid panic because of unexpected irqsxinhui pan
IP initialize ras in late_init, because of the BUGs of PSP or any other components, driver receives unexpected irqs. It is ok to add such check anyway. Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amdgpu: sdma use amdgpu_ras_feature_enable_on_bootxinhui pan
handle ras enable on boot. Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amdgpu: gmc use amdgpu_ras_feature_enable_on_bootxinhui pan
handle ras enable on boot. Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amdgpu: gfx use amdgpu_ras_feature_enable_on_bootxinhui pan
handle ras enable on boot. Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amdgpu: Introduce another ras enable functionxinhui pan
Many parts of the whole SW stack can program the ras enablement state during the boot. Now we handle that case by adding one function which check the ras flags and choose different code path. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: xinhui pan <xinhui.pan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amdgpu: Make default ras error type to nonexinhui pan
Unless IP has implemented its own ras, use ERROR_NONE as the default type. Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amd/powerplay: simplify the code of [get|set]_activity_monitor_coeffKevin Wang
use smu_update_table_with_arg to replace old code logic Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/amd/powerplay: optimization function of smu_update_tableKevin Wang
in fact, the firmware need 2 parameter: 1.table_id, 2.XferArg so change the function interface to match the firmware code Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-04-10drm/i915/dp: Expose force_dsc_enable through debugfsManasi Navare
Currently we use force_dsc_enable to force DSC from IGT, but we dont expose this value to userspace through debugfs. This patch exposes this through the same dsc_fec_support debugfs node per connector so that we can restore its value back after the tests are completed. Suggested-by: Imre Deak <imre.deak@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Lyude Paul <lyude@redhat.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190405224821.32435-1-manasi.d.navare@intel.com
2019-04-10drm/i915/dp: revert back to max link rate and lane count on eDPJani Nikula
Commit 7769db588384 ("drm/i915/dp: optimize eDP 1.4+ link config fast and narrow") started to optize the eDP 1.4+ link config, both per spec and as preparation for display stream compression support. Sadly, we again face panels that flat out fail with parameters they claim to support. Revert, and go back to the drawing board. v2: Actually revert to max params instead of just wide-and-slow. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109959 Fixes: 7769db588384 ("drm/i915/dp: optimize eDP 1.4+ link config fast and narrow") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Cc: "Lee, Shawn C" <shawn.c.lee@intel.com> Cc: Dave Airlie <airlied@gmail.com> Cc: intel-gfx@lists.freedesktop.org Cc: <stable@vger.kernel.org> # v5.0+ Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Tested-by: Albert Astals Cid <aacid@kde.org> # v5.0 backport Tested-by: Emanuele Panigati <ilpanich@gmail.com> # v5.0 backport Tested-by: Matteo Iervasi <matteoiervasi@gmail.com> # v5.0 backport Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190405075220.9815-1-jani.nikula@intel.com (cherry picked from commit f11cb1c19ad0563b3c1ea5eb16a6bac0e401f428) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2019-04-10drm/i915/icl: Fix port disable sequence for mipi-dsiVandita Kulkarni
Re-enable clock gating of DDI clocks. v2: Fix the default ddi clk state for mipi-dsi (Imre) Fixes: 1026bea00381 ("drm/i915/icl: Ungate DSI clocks") Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1553513202-13863-2-git-send-email-vandita.kulkarni@intel.com (cherry picked from commit 942d1cf48eae3fcd7e973cfb708d5c4860f0c713) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2019-04-10drm/i915/icl: Ungate ddi clocks before IO enableVandita Kulkarni
IO enable sequencing needs ddi clocks enabled. These clocks will be gated at a later point in the enable sequence. v2: Fix the commit header (Uma) v3: Remove the redundant read (Ville) Fixes: 949fc52af19e ("drm/i915/icl: add pll mapping for DSI") Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1553513202-13863-1-git-send-email-vandita.kulkarni@intel.com (cherry picked from commit c5b81a325263a891d5811aabe938c87e03db4c37) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2019-04-10drm/i915/icl: Don't warn on spurious interruptsMika Kuoppala
There is a chance we can see spurious interrupts in live now. We have more engines enabled and that with more elaborate access patterns with pm and display, increases the chances hardware just makes a social call, without anything to work on. Remove the error as we have tests to actually probe if we really miss interrupt, instead of getting spurious ones. Note that now we do write to intr_dw even with a zero value. This is considered advantegous as the write is an ack that sw is done. Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190410132124.21795-2-mika.kuoppala@linux.intel.com
2019-04-10drm/i915/icl: Handle rps interrupts without irq lockMika Kuoppala
Unlike previous gens, we already hold the irq_lock on entering the rps handler so we can't use it as it is. Make a gen11 specific rps interrupt handler without locking. v2: return early (Chris) Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190410132124.21795-1-mika.kuoppala@linux.intel.com
2019-04-10drm/i915/dp: revert back to max link rate and lane count on eDPJani Nikula
Commit 7769db588384 ("drm/i915/dp: optimize eDP 1.4+ link config fast and narrow") started to optize the eDP 1.4+ link config, both per spec and as preparation for display stream compression support. Sadly, we again face panels that flat out fail with parameters they claim to support. Revert, and go back to the drawing board. v2: Actually revert to max params instead of just wide-and-slow. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109959 Fixes: 7769db588384 ("drm/i915/dp: optimize eDP 1.4+ link config fast and narrow") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Cc: "Lee, Shawn C" <shawn.c.lee@intel.com> Cc: Dave Airlie <airlied@gmail.com> Cc: intel-gfx@lists.freedesktop.org Cc: <stable@vger.kernel.org> # v5.0+ Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Tested-by: Albert Astals Cid <aacid@kde.org> # v5.0 backport Tested-by: Emanuele Panigati <ilpanich@gmail.com> # v5.0 backport Tested-by: Matteo Iervasi <matteoiervasi@gmail.com> # v5.0 backport Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190405075220.9815-1-jani.nikula@intel.com
2019-04-10drm/i915/icl: Fix port disable sequence for mipi-dsiVandita Kulkarni
Re-enable clock gating of DDI clocks. v2: Fix the default ddi clk state for mipi-dsi (Imre) Fixes: 1026bea00381 ("drm/i915/icl: Ungate DSI clocks") Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1553513202-13863-2-git-send-email-vandita.kulkarni@intel.com
2019-04-10drm/i915/icl: Ungate ddi clocks before IO enableVandita Kulkarni
IO enable sequencing needs ddi clocks enabled. These clocks will be gated at a later point in the enable sequence. v2: Fix the commit header (Uma) v3: Remove the redundant read (Ville) Fixes: 949fc52af19e ("drm/i915/icl: add pll mapping for DSI") Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1553513202-13863-1-git-send-email-vandita.kulkarni@intel.com
2019-04-09drm/lima: include used header file explicitlyQiang Yu
To prevent build fail on some platform which does not have it in the include file chain. Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Suggested-by: Randy Dunlap <rdunlap@infradead.org> Fixes: a1d2a6339961 ("drm/lima: driver for ARM Mali4xx GPUs") Signed-off-by: Qiang Yu <yuq825@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190409003617.4470-2-yuq825@gmail.com
2019-04-09drm/lima: add missing Kconfig dependencyQiang Yu
Current implementation does not support MMU-less plarforms. Suggested-by: Randy Dunlap <rdunlap@infradead.org> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Fixes: a1d2a6339961 ("drm/lima: driver for ARM Mali4xx GPUs") Signed-off-by: Qiang Yu <yuq825@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190409003617.4470-1-yuq825@gmail.com
2019-04-09drm/mediatek: no change parent rate in round_rate() for MT2701 hdmi phyWangyan Wang
This is the third step to make MT2701 HDMI stable. We should not change the rate of parent for hdmi phy when doing round_rate for this clock. The parent clock of hdmi phy must be the same as it. We change it when doing set_rate only. Signed-off-by: Wangyan Wang <wangyan.wang@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-04-09drm/mediatek: using new factor for tvdpll for MT2701 hdmi phyWangyan Wang
This is the second step to make MT2701 HDMI stable. The factor depends on the divider of DPI in MT2701, therefore, we should fix this factor to the right and new one. Test: search ok Signed-off-by: Wangyan Wang <wangyan.wang@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-04-09drm/mediatek: remove flag CLK_SET_RATE_PARENT for MT2701 hdmi phyWangyan Wang
This is the first step to make MT2701 hdmi stable. The parent rate of hdmi phy had set by DPI driver. We should not set or change the parent rate of MT2701 hdmi phy, as a result we should remove the flags of "CLK_SET_RATE_PARENT" from the clock of MT2701 hdmi phy. Signed-off-by: Wangyan Wang <wangyan.wang@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-16 19:54:48 +0000