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path: root/drivers/gpu/drm/i915/intel_dpll_mgr.c
AgeCommit message (Expand)Author
2019-03-19drm/i915: Remove the fragile array index -> link rate mappingVille Syrjälä
2019-03-19drm/i915: Nuke icl_calc_dp_combo_pll_link()Ville Syrjälä
2019-03-19drm/i915: Remove redundant on stack dpll_hw_state from icl_get_dpll()Ville Syrjälä
2019-03-19drm/i915: Pass crtc_state down to icl dpll funcsVille Syrjälä
2019-03-19drm/i915: Remove redundant on stack dpll_hw_state from cnl_get_dpll()Ville Syrjälä
2019-03-19drm/i915: Pass crtc_state down to cnl dpll funcsVille Syrjälä
2019-03-19drm/i915: Remove redundant on stack dpll_hw_state from bxt_get_dpll()Ville Syrjälä
2019-03-19drm/i915: Pass crtc_state down to bxt dpll funcsVille Syrjälä
2019-03-19drm/i915: Remove redundant on stack dpll_hw_state from skl_get_dpll()Ville Syrjälä
2019-03-19drm/i915: Pass crtc_state down to skl dpll funcsVille Syrjälä
2019-03-19drm/i915: Don't pass crtc to intel_get_shared_dpll() and .get_dpll()Ville Syrjälä
2019-03-19drm/i915: Don't pass crtc to intel_find_shared_dpll()Ville Syrjälä
2019-03-15drm/i915/icl: remove intel_dpll_is_combophy()Lucas De Marchi
2019-03-15drm/i915/icl: split combo and tbt pll funcsLucas De Marchi
2019-03-15drm/i915/icl: split combo and mg pll disableLucas De Marchi
2019-03-15drm/i915/icl: split pll enable in three stepsLucas De Marchi
2019-03-15drm/i915/icl: split combo and mg pll enableLucas De Marchi
2019-03-13drm/i915/gen11+: First assume next platforms will inherit stuffRodrigo Vivi
2019-03-01drm/i915/icl: move MG pll hw_state readoutLucas De Marchi
2019-01-31drm/i915: Pick the first unused PLL once againVille Syrjälä
2019-01-29drm/i915/icl: keep track of unused pll while loopingLucas De Marchi
2019-01-29drm/i915/icl: use tc_port in MG_PLL macrosLucas De Marchi
2019-01-17drm/i915/dpll_mgr: switch to kernel typesJani Nikula
2019-01-14drm/i915: Markup paired operations on display power domainsChris Wilson
2018-12-03drm/i915/icl: Calculate DPLL params for DSIMadhav Chauhan
2018-10-31drm/i915/icl: Fix crash when getting DPLL of a MST encoder in TC portsJosé Roberto de Souza
2018-10-16drm/i915/icl: Refactor icl pll functionsVandita Kulkarni
2018-10-16drm/i915/icl: Use helper functions to classify the portsVandita Kulkarni
2018-10-16drm/i915/icl: Refactor get_ddi_pll using helper funcVandita Kulkarni
2018-10-08drm/i915: Fixup kernel doc for param name changesChris Wilson
2018-10-05drm/i915: Make shared dpll functions take crtc_state, v3.Maarten Lankhorst
2018-09-04drm/i915: Fix ICL+ HDMI clock readoutVille Syrjälä
2018-08-20drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separa...Manasi Navare
2018-07-27drm/i915/icl: Add TBT checks for PLL calculationsAnusha Srivatsa
2018-07-23Merge drm/drm-next into drm-intel-next-queuedRodrigo Vivi
2018-07-19drm/i915/icl: compute the TBT PLL registersPaulo Zanoni
2018-07-19Merge tag 'drm-intel-next-2018-07-09' of git://anongit.freedesktop.org/drm/dr...Dave Airlie
2018-07-05drm/i915: Mark expected switch fall-throughsGustavo A. R. Silva
2018-07-02drm/i915: Use drm_plane_mask() & co.Ville Syrjälä
2018-06-21drm/i915/icl: Do read-modify-write as needed during MG PLL programmingImre Deak
2018-06-21drm/i915/icl: Fix MG PLL setup when refclk is 38.4MHzImre Deak
2018-06-14drm/i915/icl: start adding the TBT pllPaulo Zanoni
2018-06-01drm/i915/icl: Get DDI clock for ICL based on PLLs.Manasi Navare
2018-05-07drm/i915/icl: compute the MG PLL registersPaulo Zanoni
2018-05-07drm/i915/icl: compute the combo PHY (DPLL) DP registersPaulo Zanoni
2018-05-07drm/i915/icl: compute the combo PHY (DPLL) HDMI registersPaulo Zanoni
2018-05-07drm/i915/icl: add basic support for the ICL clocksPaulo Zanoni
2018-03-27drm/i915: reorder dpll_info membersLucas De Marchi
2018-03-27drm/i915: use flags from dpll_info embedded in intel_shared_dpllLucas De Marchi
2018-03-27drm/i915: use id from intel_shared_dpll.infoLucas De Marchi
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