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path: root/drivers/gpu/drm/i915/intel_dpio_phy.c
AgeCommit message (Expand)Author
2016-12-02drm/i915: Only poll DW3_A when init DDI PHY for ports B and C.Rodrigo Vivi
2016-12-02drm/i915/glk: Implement Geminilake DDI init sequenceAnder Conselvan de Oliveira
2016-12-02drm/i915/glk: Reuse broxton code for geminilakeAnder Conselvan de Oliveira
2016-11-02drm/i915/bxt: Don't set OCL2_LDOFUSE_PWR_DIS bit in phy init sequenceAnder Conselvan de Oliveira
2016-10-28drm/i915: Address broxton phy registers based on phy and channel numberAnder Conselvan de Oliveira
2016-10-28drm/i915: Add location of the Rcomp resistor to bxt_ddi_phy_infoAnder Conselvan de Oliveira
2016-10-28drm/i915: Create a struct to hold information about the broxton physAnder Conselvan de Oliveira
2016-10-28drm/i915: Move broxton vswing sequence to intel_dpio_phy.cAnder Conselvan de Oliveira
2016-10-28drm/i915: Move DPIO phy documentation section to intel_dpio_phy.cAnder Conselvan de Oliveira
2016-10-28drm/i915: Move broxton phy code to intel_dpio_phy.cAnder Conselvan de Oliveira
2016-07-04drm/i915: Mass convert dev->dev_private to to_i915(dev)Chris Wilson
2016-04-29drm/i915: Move VLV HDMI lane reset work around logic to intel_dpio_phy.cAnder Conselvan de Oliveira
2016-04-29drm/i915: Unduplicate pre encoder enabling phy codeAnder Conselvan de Oliveira
2016-04-29drm/i915: Unduplicate VLV phy pre pll enabling codeAnder Conselvan de Oliveira
2016-04-29drm/i915: Unduplicate VLV signal level codeAnder Conselvan de Oliveira
2016-04-29drm/i915: Unduplicate CHV encoders' post pll disable codeAnder Conselvan de Oliveira
2016-04-29drm/i915: Unduplicate CHV pre-encoder enabling phy logicAnder Conselvan de Oliveira
2016-04-29drm/i915: Unduplicate CHV phy-releated pre pll enabling codeAnder Conselvan de Oliveira
2016-04-29drm/i915: Unduplicate chv_data_lane_soft_reset()Ander Conselvan de Oliveira
2016-04-29drm/i915: Unduplicate CHV signal level codeAnder Conselvan de Oliveira
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