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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)Author
2013-01-15drm/i915: Record DERRMR, FORCEWAKE and RING_CTL in error-stateChris Wilson
2012-12-17drm/i915: Implement WaSetupGtModeTdRowDispatchDaniel Vetter
2012-12-17drm/i915: Implement WaDisableHiZPlanesWhenMSAAEnabledDaniel Vetter
2012-12-10drm/i915: set the LPT FDI RX polarity reversal bit when neededPaulo Zanoni
2012-12-10drm/i915: add lpt_init_pch_refclkPaulo Zanoni
2012-12-10drm/i915: add support for mPHY destination on intel_sbi_{read, write}Paulo Zanoni
2012-11-21drm/i915: make the panel fitter work on pipes B and C on IVBPaulo Zanoni
2012-11-21drm/i915: don't intel_crt_init if DDI A has 4 lanesPaulo Zanoni
2012-11-21drm/i915: make DP work on LPT-LP machinesPaulo Zanoni
2012-11-11drm/i915: Move the remaining gtt codeBen Widawsky
2012-11-11drm/i915: flush system agent TLBs on SNBBen Widawsky
2012-11-11drm/i915: Calculate correct stolen size for GEN7+Ben Widawsky
2012-11-11drm/i915: Stop using AGP layer for GEN6+Ben Widawsky
2012-11-11drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op v3Jesse Barnes
2012-11-11drm/i915: implement WaDisablePSDDualDispatchEnable on IVB & VLVJesse Barnes
2012-11-11drm/i915: implement WaDisableVLVClockGating_VBIIssue on VLVJesse Barnes
2012-11-11drm/i915: implement WaDisableDopClockGatingisable on VLV and IVBJesse Barnes
2012-11-11drm/i915: implement WaDisableL3CacheAging on VLVJesse Barnes
2012-11-11drm/i915: fix Haswell FDI link training codePaulo Zanoni
2012-11-11drm/i915: implement WADP0ClockGatingDisableDaniel Vetter
2012-11-11drm/i915: CPT+ pch transcoder workaroundDaniel Vetter
2012-11-11drm/i915: Add SURFLIVE register definitionsVille Syrjälä
2012-11-11drm/i915: Fix display pixel format handlingVille Syrjälä
2012-11-11drm/i915: implement WaDisableRenderCachePipelinedFlushDaniel Vetter
2012-11-11drm/i915: Fix sprite offset on HSWDamien Lespiau
2012-11-11drm/i915: Fix primary plane offset on HSWDamien Lespiau
2012-11-11drm/i915: check fdi B/C lane sharing constraintDaniel Vetter
2012-10-26drm/i915: convert pipe timing definitions to transcoderPaulo Zanoni
2012-10-26drm/i915: convert CPU M/N timings to transcoderPaulo Zanoni
2012-10-26drm/i915: convert PIPE_MSA_MISC to transcoderPaulo Zanoni
2012-10-26drm/i915: convert PIPECONF to use transcoder instead of pipePaulo Zanoni
2012-10-26drm/i915: convert DDI_FUNC_CTL to transcoderPaulo Zanoni
2012-10-26drm/i915: convert PIPE_CLK_SEL to transcoderPaulo Zanoni
2012-10-26drm/i915: add TRANSCODER_EDPPaulo Zanoni
2012-10-23drm/i915: make edp panel power sequence setup more robustDaniel Vetter
2012-10-22Merge tag 'v3.7-rc2' into drm-intel-next-queuedDaniel Vetter
2012-10-19drm/i915: Consolidate ILK_DSPCLK_GATE and PCH_DSPCLK_GATEDamien Lespiau
2012-10-17drm/i915: add basic Haswell DP link train bitsPaulo Zanoni
2012-10-17drm/i915: add intel_ddi_set_pipe_settingsPaulo Zanoni
2012-10-17drm/i915: Document the multi-threaded FORCEWAKE bitsChris Wilson
2012-10-17drm/i915: Allow DRM_ROOT_ONLY|DRM_MASTER to submit privileged batchbuffersChris Wilson
2012-10-16drm/i915: Workaround to bump rc6 voltage to 450Ben Widawsky
2012-10-12drm/i915: Set guardband clipping workaround bit in the right register.Kenneth Graunke
2012-10-11drm/i915: Fix the SCC/SSC typo in the SPLL bits definitionDamien Lespiau
2012-10-10drm/i915: completely rewrite the Haswell PLL handling codePaulo Zanoni
2012-10-10drm/i915: add haswell_set_pipeconfPaulo Zanoni
2012-10-10drm/i915: enable and disable DDI_FUNC_CTL at the right timePaulo Zanoni
2012-10-10drm/i915: rewrite the LCPLL codePaulo Zanoni
2012-10-04drm/i915: implement WaDisableEarlyCull for VLV and IVBJesse Barnes
2012-10-04drm/i915: implement WaForceL3Serialization on VLV and IVBJesse Barnes
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