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path: root/drivers/gpu/drm/i915/display
AgeCommit message (Expand)Author
2019-07-30drm/i915/tgl: Add hpd interrupt handlingLucas De Marchi
2019-07-30drm/i915: use upstream version of header testsJani Nikula
2019-07-26drm/i915/tgl: select correct bit for port selectMahesh Kumar
2019-07-26drm/i915/tgl: skip setting PORT_CL_DW12_* on initializationLucas De Marchi
2019-07-19drm/i915/dsi: remove set but not used variable 'hfront_porch'YueHaibing
2019-07-19drm/i915: Remove set but not used variable 'src_y'YueHaibing
2019-07-18drm/i915/vbt: Fix VBT parsing for the PSR sectionDhinakaran Pandiyan
2019-07-18drm/i915: Make sure cdclk is high enough for DP audio on VLV/CHVVille Syrjälä
2019-07-18drm/i915/ehl: Use an id of 4 while accessing DPLL4's CR0 and CR1Vivek Kasireddy
2019-07-15drm/i915: Enable hotplug retryJosé Roberto de Souza
2019-07-15drm/i915: Add support for retrying hotplugImre Deak
2019-07-15drm/i915/ehl: Map MCC pins based on PHY, not portMatt Roper
2019-07-12drm/i915/gt: Use intel_gt as the primary object for handling resetsChris Wilson
2019-07-12drm/i915: Add modular FIAAnusha Srivatsa
2019-07-12drm/i915/display: Drop kerneldoc for 'intel_atomic_commit'Chris Wilson
2019-07-12drm/i915: Skip SINK_COUNT read on CH7511Ville Syrjälä
2019-07-12drm/i915: Propagate "_remove" function name suffix downJanusz Krzysztofik
2019-07-12drm/i915: Replace "_load" with "_probe" consequentlyJanusz Krzysztofik
2019-07-11drm/i915/tgl: Update DPLL clock reference registerJosé Roberto de Souza
2019-07-11drm/i915/tgl: Add DPLL registersLucas De Marchi
2019-07-11drm/i915/tgl: Add vbt value mapping for DDC Bus pinMahesh Kumar
2019-07-11drm/i915/tgl: port to ddc pin mappingLucas De Marchi
2019-07-11drm/i915/tgl: Add gmbus gpio pin to port mappingMahesh Kumar
2019-07-11drm/i915/gen12: MBUS B credit changeRodrigo Vivi
2019-07-11drm/i915/tgl: apply Display WA #1178 to fix type C donglesLucas De Marchi
2019-07-11drm/i915/tgl: init ddi port A-C for Tiger LakeMahesh Kumar
2019-07-11drm/i915/tgl: Add additional PHYs for Tiger LakeLucas De Marchi
2019-07-11drm/i915/tgl: Add additional ports for Tiger LakeVandita Kulkarni
2019-07-11drm/i915/tgl: Add pll managerVandita Kulkarni
2019-07-11drm/i915/tgl: Add new pll idsVandita Kulkarni
2019-07-11drm/i915/tgl: Add power well to support 4th pipeMika Kahola
2019-07-11drm/i915/tgl: Add power well supportImre Deak
2019-07-11drm/i915/tgl: rename TRANSCODER_EDP_VDSC to use on transcoder AJosé Roberto de Souza
2019-07-11drm/i915: Add 4th pipe and transcoderLucas De Marchi
2019-07-11drm/i915: Don't overestimate 4:2:0 link symbol clockVille Syrjälä
2019-07-11drm/i915: Don't pass stack garbage to pcode in the second data registerVille Syrjälä
2019-07-11drm/i915: Use intel_ types in intel_atomic_commit()Ville Syrjälä
2019-07-11drm/i915: Use intel_ types in intel_{lock,modeset}_all_pipes()Ville Syrjälä
2019-07-11drm/i915: Polish intel_atomic_track_fbs()Ville Syrjälä
2019-07-11drm/i915: Polish intel_shared_dpll_swap_state()Ville Syrjälä
2019-07-11drm/i915: Simplify modeset_get_crtc_power_domains() argumentsVille Syrjälä
2019-07-11drm/i915: Use the "display core" power domain in vlv/chv set_cdclk()Ville Syrjälä
2019-07-11drm/i915/sdvo: Fix handling if zero hbuf sizeVille Syrjälä
2019-07-10drm/i915/ehl: Enable DDI-DMatt Roper
2019-07-10drm/i915: Transition port type checks to phy checksMatt Roper
2019-07-10drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespaceMatt Roper
2019-07-10drm/i915/gen11: Program ICL_DPCLKA_CFGCR0 according to PHYMatt Roper
2019-07-10drm/i915/gen11: Start distinguishing 'phy' from 'port'Matt Roper
2019-07-10drm/i915: move intel_ddi_set_fia_lane_count to intel_tc.cLucas De Marchi
2019-07-10drm/i915: fix include order in intel_tc.*Lucas De Marchi
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