summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/amd
AgeCommit message (Collapse)Author
2018-11-05drm/amdgpu: Added a few comments for gartOak Zeng
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdkfd: Use functions from amdgpu to invalidate vmid in kfdYong Zhao
As part of the change, we stop taking the srbm lock, and start to use the same invalidation engine and software lock as amdgpu. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdgpu: Reorganize amdgpu_gmc_flush_gpu_tlb() for kfd to useYong Zhao
Add a flush_type parameter to that series of functions. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdkfd: Remove unnecessary register setting when invalidating tlb in kfdYong Zhao
Those register settings have been done in gfxhub_v1_0_program_invalidation() and mmhub_v1_0_program_invalidation(). Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdkfd: page_table_base already have the flags neededYong Zhao
The flags are added when calling amdgpu_gmc_pd_addr(). Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdkfd: Delete a duplicate statement in set_pasid_vmid_mapping()Yong Zhao
The same statement is later done in kgd_set_pasid_vmid_mapping(), so no need to do it in set_pasid_vmid_mapping(). Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Check if hubp function hooks exist before calling themCharlene Liu
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Retiring set_display_requirements in dm_pp_smu.h - part3Fatemeh Darbehani
[Why] In DCN we want direct DAL to SMU calls, with as little as possible interference by pplib. The reason for each pp_smu interface mapping to 1 SMU message is so we can have the sequencing of different SMU message in dal and shared across different OS. This will also simplify debugging as DAL owns this interaction and there's no confusion about division of ownership. [How] Separate the set_hard_min_fclk_by_freq message from the SMU messages that are sent as part of pp_rv_set_display_requirement. directly notify min dcfclk to smu part 2 Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Remove stream_res tg null check in commit planesSivapiriyanKumarasamy
[Why] TG in pipe_ctx stream resource is not null where used in commit_planes_do_stream_update since it is assigned the same time the stream is set in pipe_ctx - when the pipe is acquired. This null check produced a static code analysis warning and should be removed to avoid similar unnecessary checks in the future. [How] Remove the null check. Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdgpu: Reverse the sequence of ctx_mgr_finiRex Zhu
and vm_fini in amdgpu_driver_postclose_kms csa buffer will be created per ctx, when ctx fini, the csa buffer and va will be released. so need to do ctx_mgr fin before vm fini. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdgpu/psp: avoid hard-code fence value pre submissionHawking Zhang
Hard-code submission fence is not a sustainable way as there is more and more run-time psp kernel mode submission from driver to fw Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdkfd: Add proper prefix to functionsAmber Lin
Add amdgpu_amdkfd_ prefix to amdgpu functions served for amdkfd usage. v2: fix indentation Signed-off-by: Amber Lin <Amber.Lin@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdgpu: Remove unused function pointersAmber Lin
Remove unused function pointers in kfd2kgd structure. Signed-off-by: Amber Lin <Amber.Lin@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdkfd: Simplify kfd2kgd interfaceAmber Lin
After amdkfd module is merged into amdgpu, KFD can call amdgpu directly and no longer needs to use the function pointer. Replace those function pointers with functions if they are not ASIC dependent. Signed-off-by: Amber Lin <Amber.Lin@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdkfd: Use functions from amdgpu for setting up page table baseYong Zhao
Use the functions from amdgpu to avoid directly programming registers in amdgpu_amdkfd_gfx_v9.c. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdgpu: Expose *_setup_vm_pt_regs for kfd to useYong Zhao
kfd has the same need to set the VM page table base register, so expose them for kfd to use for better maintainability. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdkfd: Delete unnecessary register settingsYong Zhao
Those register settings have been performed in amdgpu initialization gfxhub_v1_0_setup_vmid_config() and mmhub_v1_0_setup_vmid_config(). So no need to do it again in kfd. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdgpu: increase the size of HQD EOP buffersMarek Olšák
Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdgpu: put HQD EOP buffers into VRAMMarek Olšák
This increases performance of compute queues. EOP events (PKT3_RELEASE_MEM) are stored into these buffers. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdgpu: use scheduler fault instead of reset workChristian König
Signal a fault to the scheduler on an illegal instruction or register access violation instead of kicking of the reset handler directly. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdgpu: remove illegal instruction stub from si_dma.cChristian König
Was never used. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdgpu: Revised PSP commentsJohn Clements
Revised comments in PSP SOS/Sysdriver loading sequence Signed-off-by: John Clements <clements.jm@gmail.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdgpu: fix sdma v4 ring is disabled accidentlyPhilip Yang
For sdma v4, there is bug caused by commit d4e869b6b5d6 ("drm/amdgpu: add ring test for page queue")' local variable ring is reused and changed, so amdgpu_ttm_set_buffer_funcs_status(adev, true) is skipped accidently. As a result, amdgpu_fill_buffer() will fail, kernel message: [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear memory with ring turned off. [ 25.260444] [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear memory with ring turned off. [ 25.260627] [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear memory with ring turned off. [ 25.290119] [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear memory with ring turned off. [ 25.290370] [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear memory with ring turned off. [ 25.319971] [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear memory with ring turned off. [ 25.320486] amdgpu 0000:19:00.0: [mmhub] VMC page fault (src_id:0 ring:154 vmid:8 pasid:32768, for process pid 0 thread pid 0) [ 25.320533] amdgpu 0000:19:00.0: in page starting at address 0x0000000000000000 from 18 [ 25.320563] amdgpu 0000:19:00.0: VM_L2_PROTECTION_FAULT_STATUS:0x00800134 Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdgpu: add ring test for page queueHuang Rui
We add page queue for sdma to update page table. So here it also needs ring test to verify it workable during the initialization. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdgpu: disable SDMA page queue on Vega20Evan Quan
Since we see driver loading failure on Vega20. Keep it disabled until it's ready. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdgpu/sdma4: APUs do not have a page queueAlex Deucher
Don't use the paging queue on APUs. Tested-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdgpu: use paging queue for VM page table updatesChristian König
Only for testing, not sure if we should keep it like this. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdgpu: activate paging queue on SDMA v4Christian König
Implement all the necessary stuff to get those extra rings working. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdgpu: add some [WR]REG32_SDMA macros to sdma_v4_0.cChristian König
Significantly shortens the code. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdgpu: remove SRIOV specific handling from sdma_v4_0_gfx_resumeChristian König
Just use the same code path for both SRIOV and bare metal. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdgpu: remove non gfx specific handling from sdma_v4_0_gfx_resumeChristian König
Needed to start using the paging queue. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdgpu: add basics for SDMA page queue supportChristian König
Just the common helper and a new ring in the SDMA instance. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdgpu: fix sdma v4 startup under SRIOVChristian König
Under SRIOV we were enabling the ring buffer before it was initialized. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/ttm: Rename ttm_bo_global_{init,release}() to ttm_bo_global_ref_{,}()Thomas Zimmermann
The functions ttm_bo_global_init() and ttm_bo_global_release() do not receive an argument of type struct ttm_bo_global. Both take a struct drm_global_reference that contains points to a struct ttm_bo_global_ref. Renaming them reflects this. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Fix incorrect end slope of EETFSivapiriyanKumarasamy
Force the E2 to dc_fixpt_one when E1 exceeds that value. This is the correct thing to do to avoid corruption. Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: rename cstate_pstate_watermarks_st1Bhawanpreet Lakha
cstate_pstate_watermarks_st1 -> cstate_pstate_watermarks_st Signed-off-by: vikrant mhaske <vikrant.mhaske@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: explicit uint64_t castingBhawanpreet Lakha
explicitly cast uint64_t in div64_u64_rem() Signed-off-by: vikrant mhaske <vikrant.mhaske@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: dc 3.2.02SivapiriyanKumarasamy
Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: add dccg blockDmytro Laktyushkin
This adds the hw block as well as hooks up dppclk dto programming Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: rename dccg to clk_mgrDmytro Laktyushkin
In preparation for adding the actual dccg block since the current implementation of dccg is mor eof a clock manager than a hw block Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Retiring set_display_requirements in dm_pp_smu.h - part2Fatemeh Darbehani
[Why] In DCN we want direct DAL to SMU calls, with as little as possible interference by pplib. The reason for each pp_smu interface mapping to 1 SMU message is so we can have the sequencing of different SMU message in dal and shared across different OS. This will also simplify debugging as DAL owns this interaction and there's no confusion about division of ownership. [How] Part 2: Separate set_min_deep_sleep_dcfclk message from the SMU messages that are sent as part of dm_pp_apply_clock_for_voltage_request. Directly notify min dcfclk to smu Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Retiring set_display_requirements in dm_pp_smu.h - part1Fatemeh Darbehani
[Why] In DCN we want direct DAL to SMU calls, with as little as possible interference by pplib. The reason for each pp_smu interface mapping to 1 SMU message is so we can have the sequencing of different SMU message in dal and shared across different OS. This will also simplify debugging as DAL owns this interaction and there's no confusion about division of ownership. [How] Part 1: Separate set_min_deep_Sleep_dcfclk message from the SMU messages that are sent as part of dcn10_pplib_apply_display_requirements. Notify deep sleep dcfclk to smu directly Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Add link encoder dp_ycbcr420_supported feature flagEric Bernstein
[Why] Need separate feature flag for DP 4:2:0 support, since existing flag is used for HDMI [How] Added dp_ycbcr420_supported to struct encoder_feature_support Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: fix report display count logicEric Yang
[Why] Previous logic to update display count in commit_planes_do_stream_update doesn't cover all cases. [How] Update display count as part of clock updates. Count virtual stream as active to work around headless situation. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: expose hwseq functions and add registersNevenko Stupar
Make these functions non static and define registers for future use is_lower_pipe_tree_visible(); is_upper_pipe_tree_visible(); is_pipe_tree_visible(); dcn10_program_pte_vm(); set_hdr_multiplier(); update_dchubp_dpp() find_top_pipe_for_stream() Signed-off-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: initialize dc_transfer_func->ctxDavid Francis
[Why] dc_transfer_func structs were being passed around with a null pointer, waiting for unsuspecting programmers to dereference it. [How] Initialize it Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Add support for Freesync 2 HDR and Content to Display MappingSivapiriyanKumarasamy
[Why] Freesync 2 HDR and support for HDR content outside the range of the HDR display require implementation on Dal 3 to better match Dal2. [How] Add support for Freesync HDR and mapping of source content to display ranges for better representation of HDR content. Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: split dccg clock manager into asic foldersDmytro Laktyushkin
Currently dccg contains code related to every dcn revision in a single file. This change splits out the dcn parts of code into correct folders Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: clean up base dccg structDmytro Laktyushkin
Move things not accessed outside dccg block into dce specific struct Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Freesync does not engage on some displaysHarmanprit Tatla
[Why] Current render margin time is not sufficient to compute exit frame time for most monitors. [How] Declared render margin in FPS to compute a exit frame rate that is 4 FPS above the minimum FPS required to engage FreeSync. Also did code clean-up to remove redundancies. Signed-off-by: Harmanprit Tatla <htatla@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-16 07:00:16 +0000