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Age	Commit message (Expand)	Author
2020-03-30	fpga: zynq: Remove clk_get error message for probe defer	Shubhrajyoti Datta
2019-10-04	fpga: Remove dev_err() usage after platform_get_irq()	Stephen Boyd
2019-06-05	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 285	Thomas Gleixner
2018-11-11	zynq-fpga: Only route PR via PCAP when required	Mike Looijmans
2018-10-16	fpga: mgr: add devm_fpga_mgr_create	Alan Tull
2018-05-25	fpga: manager: change api, don't use drvdata	Alan Tull
2017-03-17	fpga: zynq: Add support for encrypted bitstreams	Moritz Fischer
2017-02-10	fpga zynq: Use the scatterlist interface	Jason Gunthorpe
2017-02-10	fpga zynq: Check the bitstream for validity	Jason Gunthorpe
2017-02-10	fpga zynq: Check for errors after completing DMA	Jason Gunthorpe
2016-11-29	fpga zynq: Fix incorrect ISR state on bootup	Jason Gunthorpe
2016-11-29	fpga zynq: Remove priv->dev	Jason Gunthorpe
2016-11-29	fpga zynq: Add missing \n to messages	Jason Gunthorpe
2016-11-10	fpga-mgr: add fpga image information struct	Alan Tull
2015-10-23	fpga: zynq-fpga: Fix issue with drvdata being overwritten.	Moritz Fischer
2015-10-23	fpga: zynq-fpga: Change fw format to handle bin instead of bit.	Moritz Fischer
2015-10-23	fpga: zynq-fpga: Fix unbalanced clock handling	Moritz Fischer
2015-10-17	fpga manager: Adding FPGA Manager support for Xilinx Zynq 7000	Moritz Fischer