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2013-04-09Merge tag 'ux500-multiplatform-asoc' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/multiplatform From Linus Walleij <linus.walleij@linaro.org>: Ux500 multiplatform support. This tag builds upon the MFD-specific base tag "ux500-multiplatform-mfd". This removes all <mach/*> dependencies and makes the ux500 fully multi-platform. * tag 'ux500-multiplatform-asoc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: ARM: ux500: build hotplug.o for ARMv7-a ARM: ux500: move to multiplatform ARM: ux500: make remaining headers local ARM: ux500: make irqs.h local to platform ARM: ux500: get rid of <mach/[hardware|db8500-regs].h> staging: ste_rmi4: kill platform_data hack ARM: ux500: move mach/msp.h to <linux/platform_data/*> clk: ux500: pass clock base adresses in init call ARM: ux500: make debug macro stand-alone ARM: ux500: move debugmacro to debug includes ARM: ux500: split out prcmu initialization mfd: db8500-prcmu: drop unused includes ARM: ux500: move PM-related PRCMU functions to machine mfd: db8500-prcmu: get base address from resource mfd: prcmu: pass a base and size with the early initcall Conflicts: arch/arm/Kconfig Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-04-09Merge tag 'v3.9-rc3' into next/multiplatformArnd Bergmann
Linux 3.9-rc3 Conflicts: arch/arm/Kconfig arch/arm/mach-spear/spear3xx.c arch/arm/plat-spear/Kconfig This is a dependency for ux500/multiplatform Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-04-09Merge tag 'mxs-cleanup-3.10' of ↵Arnd Bergmann
git://git.linaro.org/people/shawnguo/linux-2.6 into next/cleanup From Shawn Guo <shawn.guo@linaro.org>: The mxs cleanup for 3.10: * Clean up timer code and move it into drivers/clocksource * Clean up icoll code and move it into drivers/irqchip * Clean up clock code to not include <mach/*> headers * Clean up rtc-stmp3xxx, mxs-lradc and mxs-saif to not include <mach/*> headers * Clean up mach-mxs code to get it prepared for multiplatform support * tag 'mxs-cleanup-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6: (26 commits) clocksource: mxs_timer: Add semicolon at end of line ARM: mxs: remove unused headers ARM: mxs: merge imx23 and imx28 into one machine_desc ARM: mxs: remove common.h ARM: mxs: move mxs_get_ocotp() into mach-mxs.c ARM: mxs: remove mm.c ARM: mxs: use debug_ll_io_init for low-level debug ARM: mxs: get ocotp base address from device tree ARM: mxs: remove system.c ARM: mxs: get reset address from device tree ARM: mxs: remove empty hardware.h ASoC: mxs-saif: remove mach header inclusion iio: mxs-lradc: remove unneeded mach header inclusion rtc: stmp3xxx: use stmp_reset_block() instead clk: mxs: remove the use of mach level IO accessor clk: mxs: get base address from device tree ARM: mxs: remove unneeded mach-types.h inclusion ARM: mxs: move icoll driver into drivers/irqchip ARM: mxs: call stmp_reset_block() in icoll ARM: mxs: get icoll base address from device tree ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-04-09Merge tag 'v3.9-rc5' into next/cleanupArnd Bergmann
This is a dependency for the mxs/cleanup branch. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-04-09Merge branch 'tegra/fixes' into next/cleanupArnd Bergmann
This is a dependency for tegra/cleanups Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-04-09Merge tag 'tegra-for-3.10-fixes' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/fixes-non-critical From Stephen Warren <swarren@wwwdotorg.org>: ARM: tegra: minor fixes This branch contains a variety of small build and run-time fixes that weren't important enough for 3.9. * Enable CPU errata WARs in secondary reset handler as a preparation for multi-platform support, and a related fix. * Don't touch DBLGAR in reset/resume handlers, so enable the code to run on A15 cores. * Minor build fixes. * A fix to the Tegra clock driver. * Some error-handling fixes. This branch is based on the previous fixes-for-mmc pull request. * tag 'tegra-for-3.10-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: ARM: tegra: powergate: Don't error out if new state == old state ARM: tegra: Export tegra_powergate_sequence_power_up() memory: tegra30: Fix build error w/o PM ARM: tegra: fix ignored return value of regulator_enable ARM: tegra: fix the logical detection of power on sequence of warm boot CPUs ARM: tegra: Fix unchecked return value ARM: tegra: don't unlock MMIO access to DBGLAR clk: tegra: No 7.1 super clk dividers on Tegra20 ARM: tegra: remove save/restore of CPU diag register ARM: tegra: add CPU errata WARs to Tegra reset handler ARM: dts: tegra: fix the activate polarity of cd-gpio in mmc host Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-04-08clk: mvebu: Fix valid value range checking for cpu_freq_selectAxel Lin
cpu_freq_select is used as array subscript, thus the valid value range is 0 ... ARRAY_SIZE() - 1. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: fixed up trivial merge issues]
2013-04-08clk: Fixup locking issues for clk_set_parentUlf Hansson
Updating the clock tree topology must be protected with the spinlock when doing clk_set_parent, otherwise we can not handle the migration of the enable_count in a safe manner. While issuing the .set_parent callback to make the clk-hw perform the switch to the new parent, we can not hold the spinlock since it is must be allowed to be slow path. This complicates error handling, but is still possible to achieve. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Cc: Rajagopal Venkat <rajagopal.venkat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-04-08clk: Fixup errorhandling for clk_set_parentUlf Hansson
Fixup the broken feature of allowing reparent of a clk to the orhpan list and vice verse. When operating on a single-parent clk, the .set_parent callback for the clk hw is optional to implement, but for a multi-parent clk it is mandatory. Moreover improve the errorhandling by verifying the prerequisites before triggering clk notifiers. This will prevent unnecessary rollback with ABORT_RATE_CHANGE. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Cc: Rajagopal Venkat <rajagopal.venkat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-04-08clk: Restructure code for __clk_reparentUlf Hansson
Split __clk_reparent into three pieces, one for doing the actual reparent for updating the clock tree topology, one for the COMMON_CLK_DEBUG code and one for doing the rate recalculation. This patch also makes it possible to hold the spinlock over the update of the clock tree topology, which could not be done before when both debugfs updates and clock rate updates was done within the same function. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Cc: Rajagopal Venkat <rajagopal.venkat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-04-09Merge commit 'v3.9-rc5' into next/clk-exynosKukjin Kim
Conflicts: arch/arm/boot/dts/exynos4.dtsi arch/arm/boot/dts/exynos5440.dtsi
2013-04-08Merge tag 'omap-for-v3.10/fixes-non-critical-signed' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/fixes-non-critical From Tony Lindgren <tony@atomide.com>: Non critical omap fixes for v3.10 merge window. A big chunk of these fixes are needed to support omap5 es2 version that includes PM features while the earlier version es1 did not. * tag 'omap-for-v3.10/fixes-non-critical-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP2+: fix typo "CONFIG_BRIDGE_DVFS" ARM: OMAP1: remove "config MACH_OMAP_HTCWIZARD" ARM: OMAP: dpll: enable bypass clock only when attempting dpll bypass ARM: OMAP2+: powerdomain: avoid testing whether an unsigned char is less than 0 ARM: OMAP2+: hwmod: Remove unused _HWMOD_WAKEUP_ENABLED flag ARM: OMAP2+: am335x: Change the wdt1 func clk src to per_32k clk ARM: OMAP2+: AM33xx: hwmod: Add missing sysc definition to wdt1 entry Contains an update to 3.9-rc5 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-04-08clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}Tushar Behera
In legacy setup, sclk_mmc{0,1,2,3} used PRE_RATIO bit-field (8-bit wide) instead of RATIO bit-field (4-bit wide) for dividing clock rate. With current common clock setup, we are using RATIO bit-field which is creating FIFO read errors while accessing eMMC. Changing over to use PRE_RATIO bit-field fixes this issue. dwmmc_exynos 12200000.dwmmc0: data FIFO error (status=00008020) mmcblk0: error -5 transferring data, sector 1, nr 7, cmd response 0x900, card status 0x0 end_request: I/O error, dev mmcblk0, sector 1 Signed-off-by: Tushar Behera <tushar.behera@linaro.org> CC: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-08clk: exynos4: export clocks required for fimc-isSylwester Nawrocki
This patch adds clock indexes for ACLK_DIV0, ACLK_DIV1, ACLK_400_MCUISP, ACLK_MCUISP_DIV0, ACLK_MCUISP_DIV1, DIVACLK_400_MCUISP and DIVACLK_200 so these clocks are available to the consumers (Exynos4x12 FIMC-IS subsystem). While at it, indentation of the mux clocks table is corrected. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-08clk: samsung: Fix compilation errorSachin Kamat
Fixes the below compilation error during non-dt build. drivers/clk/samsung/clk.c: In function 'samsung_clk_of_register_fixed_ext': drivers/clk/samsung/clk.c:252:2: error: implicit declaration of function 'for_each_matching_node_and_match' [-Werror=implicit-function-declaration] drivers/clk/samsung/clk.c:252:60: error: expected ';' before '{' token Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-08ARM: ux500: get rid of <mach/[hardware|db8500-regs].h>Linus Walleij
This removes <mach/hardware.h> and <mach/db8500-regs.h> from the Ux500, merging them into the local include "db8500-regs.h" in mach-ux500. There is some impact outside the ux500 machine, but most of it is dealt with in earlier patches. Contains portions of a clean-up patch from Arnd Bergmann. Cc: Samuel Ortiz <sameo@linux.intel.com> Cc: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-08clk: ux500: pass clock base adresses in init callLinus Walleij
The ux500 clock driver was including <mach/db8500-regs.h> which will not work when building for multiplatform support since <mach/*> is going away. Pass the base adresses in the init call instead. Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: Mike Turquette <mturquette@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-04clk: tegra: fix enum tegra114_clk to match bindingStephen Warren
A gap exists in the binding's clock ID definitions. Fix the clock driver to be consistent. This allows pclk to be looked up through device tree and prevents: ERROR: could not get clock /pmc:pclk(0) Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: Remove forced clk_enable of uartdPeter De Schrijver
The UART driver enables the console uart clock, so we don't need to do that anymore in this file. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: devicetree match for nvidia,tegra114-carPeter De Schrijver
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: Implement clocks for Tegra114Peter De Schrijver
Implement clocks for Tegra114. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: Workaround for Tegra114 MSENC problemPeter De Schrijver
Workaround a hardware bug in MSENC during clock enable. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: Add flags to tegra_clk_periph()Peter De Schrijver
We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag, most notably mselect, which is a bridge between AXI and most peripherals. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: Add new fields and PLL types for Tegra114Peter De Schrijver
Tegra114 introduces new PLL types. This requires new clocktypes as well as some new fields in the pll structure. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: move from a lock bit idx to a lock maskPeter De Schrijver
PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits. So switch to a lock mask to be able to test both at the same time. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: Add PLL post divider tablePeter De Schrijver
Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider. Introduce a table based approach and switch PLLU to it. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLEPeter De Schrijver
Tegra114 PLLC2 and PLLC3 don't have a lock enable bit. The lock bits are always functional. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: Add TEGRA_PLL_BYPASS flagPeter De Schrijver
Not all PLLs in Tegra114 have a bypass bit. Adapt the common code to only use this bit when available. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: Refactor PLL programming codePeter De Schrijver
Refactor the PLL programming code to make it useable by the new PLL types introduced by Tegra114. The following changes were done: * Split programming the PLL into updating m,n,p and updating cpcon * Move locking from _update_pll_cpcon() to clk_pll_set_rate() * Introduce _get_pll_mnp() helper * Move check for identical m,n,p values to clk_pll_set_rate() * struct tegra_clk_pll_freq_table will always contain the values as defined by the hardware. * Simplify the arguments to clk_pll_wait_for_lock() * Split _tegra_clk_register_pll() Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: provide dummy cpu car opsPeter De Schrijver
tegra_boot_secondary() relies on some of the car ops. This means having an uninitialized tegra_cpu_car_ops will lead to an early boot panic. Providing a dummy struct avoids this and makes adding Tegra114 clock support in a bisectable way a lot easier. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: defer application of init tableStephen Warren
The Tegra clock driver is initialized during the ARM machine descriptor's .init_irq() hook. It can't be initialized earlier, since dynamic memory usage is required. It can't be initialized later, since the .init_timer() hook needs the clocks initialized. However, at this time, udelay() doesn't work. The Tegra clock initialization table may enable some PLLs. Enabling a PLL may require usage of udelay(). Hence, this can't happen right when the clock driver is initialized. To solve this, separate the clock driver initialization from the clock table processing, so they can execute at separate times. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: Fix cdev1 and cdev2 IDsPrashant Gaikwad
Correct IDs for cdev1 and cdev2 are 94 and 93 respectively. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: split into separate driver and device-tree patches] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: Make gr2d and gr3d clocks children of pll_cThierry Reding
By default these clocks are children of pll_m, but in downstream kernels they are reparented to pll_c. While at it, decrease their frequencies to 300 MHz because the defaults aren't in the specified range. gr2d can reportedly run at much higher frequencies, but 300 MHz works and is a more conservative default. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: Export peripheral reset functionsThierry Reding
The tegra_periph_reset_assert() and tegra_periph_reset_deassert() functions can be used by drivers to reset peripherals. In order to allow such drivers to be built as modules, export the functions. Note that this restores the status quo as the functions were exported before the move to the drivers/clk tree. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: Fix periph_clk_to_bit macroYen Lin
The parameter name should be "gate", not "periph". This worked, however, because it happens that everywhere periph_clk_to_bit is called, "gate" was in the local scope. Signed-off-by: Yen Lin <yelin@nvidia.com> Signed-off-by: Andrew Chew <achew@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04Merge remote-tracking branch 'linaro_mturquette_linux/clk-for-3.10' into ↵Stephen Warren
for-3.10/clk
2013-04-04Merge branch 'for-3.10/soc' into for-3.10/clkStephen Warren
2013-04-04clk: sunxi: drop an unnecesary kmallocEmilio López
clk_register will copy this information, so we can just use a normal array and do one less dynamic allocation. Signed-off-by: Emilio López <emilio@elopez.com.ar> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-04-04clk: sunxi: drop CLK_IGNORE_UNUSEDEmilio López
This flag was in place to prevent important clocks from getting gated while they had no users. Now that the UART driver supports clocks properly, we can drop this. Signed-off-by: Emilio López <emilio@elopez.com.ar> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-04-04clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gatesEmilio López
This patchset adds DT support for all the AXI, AHB, APB0 and APB1 gates present on sunxi SoCs. Signed-off-by: Emilio López <emilio@elopez.com.ar> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-04-04clk: exynos5250: register display block gate clocks to common clock frameworkLeela Krishna Amudala
Add gate clocks for fimd, mie, dsim, dp, mixer and hdmi. Register it to common clock framework. Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04clk: exynos4: Add support for SoC-specific register save listTomasz Figa
This patch extends suspend/resume support for SoC-specific registers to handle differences in register sets on particular SoCs. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04clk: exynos4: Add missing registers to suspend save listTomasz Figa
This patch adds missing clock control registers to the list of registers that should be saved across system suspend. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04clk: exynos4: Remove E4X12 prefix from SRC_DMC registerTomasz Figa
This register is present on all Exynos4 SoCs and so the prefix is misleading. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04clk: exynos4: Add E4210 prefix to GATE_IP_PERIR registerTomasz Figa
This definition is specific for Exynos4210 (which has another location than the same register on Exynos4x12 SoCs) and so needs appropriate prefix. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04clk: exynos4: Add E4210 prefix to LCD1 clock registersTomasz Figa
This patch adds E4210 prefix to all registers related to LCD1 clock domain, because they are present only on Exynos4210. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04clk: exynos4: Remove SoC-specific registers from save listTomasz Figa
Current clock save list is shared for all Exynos4 SoCs, so it must contain only registers present in all supported SoCs, because accessing unavailable registers might have undefined effect. This patch removes registers specific for particular SoCs from shared save list, as they should be supported by separate SoC-specific lists. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04clk: exynos4: Use SRC_MASK_PERIL{0,1} definitionsTomasz Figa
There are definitions of SRC_MASK_PERIL0 and SRC_MASK_PERIL1 registers, but they are not used for clock definitions. This patch modifies related clock definitions to use defined macros instead of numeric offsets. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04clk: exynos4: Define {E,V}PLL registersTomasz Figa
This patch adds preprocessor definitions of EPLL and VPLL registers and replaces all occurences of offsets of related registers with new definitions. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04clk: exynos4: Add missing mout_sata on Exynos4210Tomasz Figa
This patch adds missing mout_sata that is a parent of div_sata clock. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-21 07:51:26 +0000