summaryrefslogtreecommitdiff
path: root/drivers/clk/tegra
AgeCommit message (Expand)Author
2016-06-30clk: tegra: Initialize UTMI PLL when enabling PLLUAndrew Bresticker
2016-06-23clk: tegra: Micro-optimize Tegra210 clock setupThierry Reding
2016-06-23clk: tegra: Make sor_safe the parent of dpaux and dpaux1Thierry Reding
2016-06-22clk: tegra: Mark timer clock as criticalThierry Reding
2016-06-17clk: tegra: Enable sor1 and sor1_src on Tegra210Thierry Reding
2016-06-17clk: tegra: Squash sor1 safe/brick/src into a single muxThierry Reding
2016-06-17clk: tegra: Disable spread spectrum on pll_d2Thierry Reding
2016-06-10clk: tegra: Fixup post dividers on Tegra210Thierry Reding
2016-05-27remove lots of IS_ERR_VALUE abusesArnd Bergmann
2016-05-20Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds
2016-05-18Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/a...Linus Torvalds
2016-05-09Merge tag 'tegra-for-4.7-phy' of git://git.kernel.org/pub/scm/linux/kernel/gi...Arnd Bergmann
2016-05-02Merge tag 'tegra-for-4.7-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...Stephen Boyd
2016-04-28clk: tegra: dfll: Reformat CVB frequency tableThierry Reding
2016-04-28clk: tegra: dfll: Properly clean up on failure and removalThierry Reding
2016-04-28clk: tegra: dfll: Make code more comprehensibleThierry Reding
2016-04-28clk: tegra: dfll: Reference CVB table instead of copying dataThierry Reding
2016-04-28clk: tegra: dfll: Update kerneldocThierry Reding
2016-04-28clk: tegra: Fix PLL_U post divider and initial rate on Tegra30Lucas Stach
2016-04-28clk: tegra: Initialize PLL_C to sane rate on Tegra30Lucas Stach
2016-04-28clk: tegra: Fix pllre Tegra210 and add pll_re_out1Rhyland Klein
2016-04-28clk: tegra: Add sor_safe clockThierry Reding
2016-04-28clk: tegra: dpaux and dpaux1 are fixed factor clocksThierry Reding
2016-04-28clk: tegra: Add dpaux1 clockThierry Reding
2016-04-28clk: tegra: Use correct parent for dpaux clockThierry Reding
2016-04-28clk: tegra: Add fixed factor peripheral clock typeThierry Reding
2016-04-28clk: tegra: Special-case mipi-cal parent on Tegra114Thierry Reding
2016-04-28clk: tegra: Remove trailing blank lineThierry Reding
2016-04-28clk: tegra: Constify peripheral clock registersThierry Reding
2016-04-28clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLsAndrew Bresticker
2016-04-28treewide: Fix typos in printkMasanari Iida
2016-03-29clk: tegra: Make reset_control_ops constPhilipp Zabel
2016-03-02clk: tegra: Remove CLK_IS_ROOTStephen Boyd
2016-02-02clk: tegra: super: Fix sparse warnings for functions not declared as staticJon Hunter
2016-02-02clk: tegra: Fix sparse warnings for functions not declared as staticJon Hunter
2016-02-02clk: tegra: Fix sparse warning for pll_mJon Hunter
2016-02-02clk: tegra: Use definition for pll_u override bitJon Hunter
2016-02-02clk: tegra: Fix warning caused by pll_u failing to lockJon Hunter
2016-02-02clk: tegra: Fix clock sources for Tegra210 EMCJon Hunter
2016-02-02clk: tegra: Add the APB2APE audio clock on Tegra210Jon Hunter
2016-02-02clk: tegra: Add missing of_node_put()Amitoj Kaur Chawla
2016-02-02clk: tegra: Fix PLLE SS coefficientsMark Kuo
2016-02-02clk: tegra: Fix typos around clearing PLLE bits during enableRhyland Klein
2016-02-02clk: tegra: Do not disable PLLE when under hardware controlMark Kuo
2016-02-02clk: tegra: Fix pllx dyn step calculationRhyland Klein
2016-02-02clk: tegra: pll: Fix potential sleeping-while-atomicAndrew Bresticker
2016-02-02clk: tegra: Fix the misnaming of nvenc from msencRhyland Klein
2016-02-02clk: tegra: Fix naming of MISC registersRhyland Klein
2016-01-25clk: tegra: Remove improper flags for lock_enableRhyland Klein
2016-01-25clk: tegra: Fix divider on VI_I2CRhyland Klein
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-02 05:04:09 +0000