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Age	Commit message (Expand)	Author
2019-11-11	clk: tegra: Fix build error without CONFIG_PM_SLEEP	YueHaibing
2019-11-11	clk: tegra: Add suspend and resume support on Tegra210	Sowjanya Komatineni
2019-11-11	clk: tegra: Use fence_udelay() during PLLU init	Sowjanya Komatineni
2019-11-11	clk: tegra: Reimplement SOR clocks on Tegra210	Thierry Reding
2019-11-11	clk: tegra: Rename sor0_lvds to sor0_out	Thierry Reding
2019-11-11	clk: tegra: Remove last remains of TEGRA210_CLK_SOR1_SRC	Thierry Reding
2019-07-17	Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...	Linus Torvalds
2019-06-28	Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...	Linus Torvalds
2019-06-25	clk: tegra: Do not enable PLL_RE_VCO on Tegra210	Thierry Reding
2019-06-25	clk: tegra: Warn if an enabled PLL is in IDDQ	Thierry Reding
2019-06-25	clk: tegra: Do not warn unnecessarily	Thierry Reding
2019-06-25	clk: tegra210: fix PLLU and PLLU_OUT1	JC Kuo
2019-06-14	clk: tegra210: Fix default rates for HDA clocks	Jon Hunter
2019-05-30	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	Thomas Gleixner
2019-04-23	clk: core: replace clk_{readl,writel} with {readl,writel}	Jonas Gorski
2018-12-14	clk: tegra: Fix maximum audio sync clock for Tegra124/210	Jon Hunter
2018-10-16	clk: tegra210: Include size.h for compilation ease	Stephen Boyd
2018-10-16	clk: tegra: Fixes for MBIST work around	Joseph Lo
2018-07-25	clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks	Peter De-Schrijver
2018-05-18	clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20	Dmitry Osipenko
2018-03-12	clk: tegra: Mark HCLK, SCLK and EMC as critical	Dmitry Osipenko
2018-03-08	clk: tegra: MBIST work around for Tegra210	Peter De Schrijver
2018-03-08	clk: tegra: Add la clock for Tegra210	Peter De Schrijver
2017-11-01	clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init()	Nicolin Chen
2017-10-19	clk: tegra: Fix sor1_out clock implementation	Thierry Reding
2017-08-23	clk: tegra: Fix Tegra210 PLLU initialization	Alex Frid
2017-08-23	clk: tegra: Correct Tegra210 UTMIPLL poweron delay	Alex Frid
2017-08-23	clk: tegra: Re-factor T210 PLLX registration	Alex Frid
2017-08-23	clk: tegra: don't warn for pll_d2 defaults unnecessarily	Peter De Schrijver
2017-08-23	clk: tegra: Fix T210 effective NDIV calculation	Alex Frid
2017-08-23	clk: tegra210: remove non-existing VFIR clock	Peter De Schrijver
2017-08-23	clk: tegra: disable SSC for PLL_D2	Peter De Schrijver
2017-04-04	clk: tegra: Don't reset PLL-CX if it is already enabled	Jon Hunter
2017-04-04	clk: tegra: Add missing Tegra210 clocks	Peter De Schrijver
2017-03-20	clk: tegra: Mark TEGRA210_CLK_DBGAPB as always on	Peter De Schrijver
2017-03-20	clk: tegra: Add SATA seq input control	Peter De Schrijver
2017-03-20	clk: tegra: Add Tegra210 special resets	Peter De Schrijver
2017-03-20	clk: tegra: Rework pll_u	Peter De Schrijver
2017-03-20	clk: tegra: Handle UTMIPLL IDDQ	Peter De Schrijver
2017-03-20	clk: tegra: Add aclk	Peter De Schrijver
2017-03-20	clk: tegra: Define Tegra210 DMIC clocks	Peter De Schrijver
2017-03-20	clk: tegra: Define Tegra210 DMIC sync clocks	Peter De Schrijver
2017-03-20	clk: tegra: Add CEC clock	Peter De Schrijver
2017-03-20	clk: tegra: Correct tegra210_pll_fixed_mdiv_cfg rate calculation	Peter De Schrijver
2017-03-20	clk: tegra: Don't warn for PLL defaults unnecessarily	Peter De Schrijver
2017-03-20	clk: tegra: Remove non-existing pll_m_out1 clock	Peter De Schrijver
2017-03-20	clk: tegra: Fix ISP clock modelling	Peter De Schrijver
2017-03-20	clk: tegra: Fix pll_a1 iddq register, add pll_a1	Peter De Schrijver
2016-06-30	clk: tegra: Initialize UTMI PLL when enabling PLLU	Andrew Bresticker
2016-06-23	clk: tegra: Micro-optimize Tegra210 clock setup	Thierry Reding