| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-11-11 | clk: tegra: clk-super: Fix to enable PLLP branches to CPU | Sowjanya Komatineni |
| 2019-05-30 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201 | Thomas Gleixner |
| 2018-03-12 | clk: tegra: Mark HCLK, SCLK and EMC as critical | Dmitry Osipenko |
| 2017-11-01 | clk: tegra: Mark APB clock as critical | Jon Hunter |
| 2017-08-23 | clk: tegra: Re-factor T210 PLLX registration | Alex Frid |
| 2016-02-02 | clk: tegra: super: Fix sparse warnings for functions not declared as static | Jon Hunter |
| 2015-12-17 | clk: tegra: Add Super Gen5 Logic | Bill Huang |
| 2015-08-25 | Merge tag 'tegra-for-4.3-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi... | Stephen Boyd |
| 2015-07-20 | clk: tegra: Properly include clk.h | Stephen Boyd |
| 2015-07-16 | clk: tegra: Add the DFLL as a possible parent of the cclk_g clock | Tuomas Tynkkynen |
| 2014-02-17 | clk: tegra: cclk_lp has a pllx/2 divider | Andrew Bresticker |
| 2013-11-26 | clk: tegra: introduce common gen4 super clock | Peter De Schrijver |
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index : linux.git | |
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