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path: root/drivers/clk/tegra/clk-pll.c
AgeCommit message (Expand)Author
2020-05-12clk: tegra: pll: Add pre/post rate-change hooksDmitry Osipenko
2019-11-11clk: tegra: pll: Save and restore pll contextSowjanya Komatineni
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner
2019-04-25clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides dividerDmitry Osipenko
2019-04-19clk: tegra: Don't enable already enabled PLLsDmitry Osipenko
2018-12-14clk: tegra: Return the exact clock rate from clk_round_rateRobert Yang
2018-03-12clk: tegra: Fix pll_u rate configurationMarcel Ziswiler
2017-08-23clk: tegra: Fix T210 PLLRE registrationAlex Frid
2017-08-23clk: tegra: Update T210 PLLSS (D2/DP) registrationAlex Frid
2017-08-23clk: tegra: Re-factor T210 PLLX registrationAlex Frid
2017-08-23clk: tegra: change post IDDQ release delay to 5usPeter De Schrijver
2017-08-23clk: tegra: Init cfg structure in _get_pll_mnpPeter De Schrijver
2017-08-23clk: tegra: Enable PLL_SS for Tegra210Peter De Schrijver
2017-08-23clk: tegra: fix SS control on PLL enable/disablePeter De Schrijver
2017-03-20clk: tegra: Rework pll_uPeter De Schrijver
2016-06-30clk: tegra: Initialize UTMI PLL when enabling PLLUAndrew Bresticker
2016-04-28clk: tegra: Fix pllre Tegra210 and add pll_re_out1Rhyland Klein
2016-02-02clk: tegra: Fix PLLE SS coefficientsMark Kuo
2016-02-02clk: tegra: Fix typos around clearing PLLE bits during enableRhyland Klein
2016-02-02clk: tegra: Do not disable PLLE when under hardware controlMark Kuo
2016-02-02clk: tegra: pll: Fix potential sleeping-while-atomicAndrew Bresticker
2015-12-17clk: tegra: Read correct IDDQ register in PLL_SS registrationBill Huang
2015-12-17clk: tegra: Fix WARN_ON in PLL_RE registrationBill Huang
2015-12-17clk: tegra: pll: Fix issues with rates for VCO PLLsAndrew Bresticker
2015-12-17clk: tegra: Add support for Tegra210 clocksRhyland Klein
2015-12-17clk: tegra: pll: Add logic for SSBill Huang
2015-12-17clk: tegra: pll: Add dyn_ramp callbackRhyland Klein
2015-12-17clk: tegra: pll: Add Set_default logicBill Huang
2015-12-17clk: tegra: pll: Adjust vco_min if SDM presentBill Huang
2015-12-17clk: tegra: pll: Add support for PLLMB for Tegra210Rhyland Klein
2015-12-17clk: tegra: pll: Add specialized logic for Tegra210Rhyland Klein
2015-11-20clk: tegra: pll: Update PLLM handlingDanny Huang
2015-11-20clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rateRhyland Klein
2015-11-20clk: tegra: pll: Add code to handle if resets are supported by PLLBill Huang
2015-11-20clk: tegra: pll: Add logic for out-of-table rates for T210Rhyland Klein
2015-11-20clk: tegra: pll: Add logic for handling SDM dataRhyland Klein
2015-11-20clk: tegra: pll: Don't unconditionally set LOCK flagsRhyland Klein
2015-11-20clk: tegra: pll: Update warning messageRhyland Klein
2015-11-20clk: tegra: pll: Simplify clk_enable_pathRhyland Klein
2015-11-20clk: tegra: pll: Add tegra_pll_wait_for_lock to clk headerRhyland Klein
2015-11-20clk: tegra: Constify pdiv-to-hw mappingsThierry Reding
2015-11-18clk: tegra: Miscellaneous coding style cleanupsThierry Reding
2015-08-24clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)Stephen Boyd
2015-08-24clk: tegra: Convert to clk_hw based provider APIsStephen Boyd
2015-07-20clk: tegra: Properly include clk.hStephen Boyd
2015-04-10clk: tegra: Remove needless initializationsThierry Reding
2015-04-10clk: tegra: Various whitespace cleanupsThierry Reding
2015-02-02clk: tegra: Add support for the Tegra132 CAR IP blockPaul Walmsley
2015-02-02clk: tegra: Fix order of arguments in WARNTomeu Vizoso
2014-07-08clk: tegra: Use XUSB-compatible SATA PLL sequenceMikko Perttunen