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path: root/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
AgeCommit message (Expand)Author
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282Thomas Gleixner
2019-05-15clk: Remove io.h from clk-provider.hStephen Boyd
2018-12-04clk: sunxi-ng: h3: Allow parent change for ve clockJernej Skrabec
2018-12-03clk: sunxi-ng: h3/h5: Fix CSI_MCLK parentChen-Yu Tsai
2018-08-27clk: sunxi-ng: h3/h5: Add max. rate constraint to pll-videoJernej Skrabec
2018-03-02clk: sunxi-ng: h3: h5: Allow some clocks to set parent rateJernej Skrabec
2018-03-02clk: sunxi-ng: h3: h5: Add minimal rate for video PLLJernej Skrabec
2017-10-13clk: sunxi-ng: sun8i: h3: Use sigma-delta modulation for audio PLLChen-Yu Tsai
2017-09-17clk: sunxi-ng: add CLK_SET_RATE_PARENT flag to H3 GPU clockIcenowy Zheng
2017-09-17clk: sunxi-ng: add CLK_SET_RATE_UNGATE to all H3 PLLsIcenowy Zheng
2017-08-23Merge tag 'sunxi-clk-for-4.14-2' of https://git.kernel.org/pub/scm/linux/kern...Stephen Boyd
2017-08-04clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3Icenowy Zheng
2017-08-04clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate changeChen-Yu Tsai
2017-07-21clk: Convert to using %pOF instead of full_nameRob Herring
2017-06-07clk: sunxi-ng: Support multiple variable pre-dividersChen-Yu Tsai
2017-03-06clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driverIcenowy Zheng
2017-01-02clk: sunxi-ng: fix PLL_CPUX adjusting on H3Ondrej Jirman
2016-11-11clk: sunxi-ng: sun8i-h3: Set CLK_SET_RATE_PARENT for audio module clocksChen-Yu Tsai
2016-09-14Merge tag 'sunxi-clk-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/...Stephen Boyd
2016-08-29clk: sunxi-ng: Fix wrong reset register offsetsJorik Jonker
2016-08-25clk: sunxi-ng: mux: support fixed pre-dividers on multiple parentsChen-Yu Tsai
2016-07-11clk: sunxi-ng: h3: Fix audio clock divider offsetMaxime Ripard
2016-07-08clk: sunxi-ng: Add H3 clocksMaxime Ripard
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 22:35:49 +0000