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path: root/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
AgeCommit message (Expand)Author
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282Thomas Gleixner
2019-05-15clk: Remove io.h from clk-provider.hStephen Boyd
2019-01-28clk: sunxi: A31: Fix wrong AHB gate numberAndre Przywara
2018-02-19clk: sunxi-ng: a31: Fix CLK_OUT_* clock opsChen-Yu Tsai
2017-10-13clk: sunxi-ng: sun6i: Use sigma-delta modulation for audio PLLChen-Yu Tsai
2017-09-29clk: sunxi-ng: sun6i: Rename HDMI DDC clock to avoid name collisionChen-Yu Tsai
2017-07-21clk: Convert to using %pOF instead of full_nameRob Herring
2017-06-07clk: sunxi-ng: Support multiple variable pre-dividersChen-Yu Tsai
2017-05-14clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offsetChen-Yu Tsai
2017-03-06clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clockChen-Yu Tsai
2017-01-02clk: sunxi-ng: A31: Fix spdif clock registerMarcus Cooper
2016-11-21clk: sunxi-ng: sun6i-a31: Enable PLL-MIPI LDOs when ungating itChen-Yu Tsai
2016-10-19clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parentChen-Yu Tsai
2016-09-16clk: sunxi-ng: sun6i-a31: Fix register offset for mipi-csi clkChen-Yu Tsai
2016-09-16clk: sunxi-ng: sun6i-a31: set CLK_SET_RATE_UNGATE for all PLLsChen-Yu Tsai
2016-09-16clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output clocksChen-Yu Tsai
2016-08-25clk: sunxi-ng: Add A31/A31s clocksChen-Yu Tsai
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