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Age	Commit message (Expand)	Author
2018-02-19	clk: sunxi-ng: a31: Fix CLK_OUT_* clock ops	Chen-Yu Tsai
2017-10-13	clk: sunxi-ng: sun6i: Use sigma-delta modulation for audio PLL	Chen-Yu Tsai
2017-09-29	clk: sunxi-ng: sun6i: Rename HDMI DDC clock to avoid name collision	Chen-Yu Tsai
2017-07-21	clk: Convert to using %pOF instead of full_name	Rob Herring
2017-06-07	clk: sunxi-ng: Support multiple variable pre-dividers	Chen-Yu Tsai
2017-05-14	clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset	Chen-Yu Tsai
2017-03-06	clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clock	Chen-Yu Tsai
2017-01-02	clk: sunxi-ng: A31: Fix spdif clock register	Marcus Cooper
2016-11-21	clk: sunxi-ng: sun6i-a31: Enable PLL-MIPI LDOs when ungating it	Chen-Yu Tsai
2016-10-19	clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parent	Chen-Yu Tsai
2016-09-16	clk: sunxi-ng: sun6i-a31: Fix register offset for mipi-csi clk	Chen-Yu Tsai
2016-09-16	clk: sunxi-ng: sun6i-a31: set CLK_SET_RATE_UNGATE for all PLLs	Chen-Yu Tsai
2016-09-16	clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output clocks	Chen-Yu Tsai
2016-08-25	clk: sunxi-ng: Add A31/A31s clocks	Chen-Yu Tsai