summaryrefslogtreecommitdiff
path: root/drivers/clk/st/clkgen-pll.c
AgeCommit message (Expand)Author
2015-10-08drivers: clk: st: Correct the pll-type for A9 for stih418Gabriel Fernandez
2015-10-08drivers: clk: st: PLL rate change implementation for DVFSGabriel Fernandez
2015-10-08drivers: clk: st: Support for enable/disable in Clockgen PLLsGabriel Fernandez
2015-09-17drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_xGabriel Fernandez
2015-08-24clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)Stephen Boyd
2015-07-28Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd
2015-07-20clk: st: Include clk.hStephen Boyd
2015-07-06drivers: clk: st: Add CLK_GET_RATE_NOCACHE flag to clocksPankaj Dev
2015-05-14clk: st: Silence sparse warningsStephen Boyd
2015-04-01clk: constify of_device_id arrayFabian Frederick
2014-07-28clk: st: STiH407: Support for clockgenA9Gabriel FERNANDEZ
2014-07-28clk: st: STiH407: Support for clockgenC0Gabriel FERNANDEZ
2014-07-28clk: st: STiH407: Support for clockgenA0Gabriel FERNANDEZ
2014-07-28clk: st: use static const for clkgen_pll_data tablesGabriel FERNANDEZ
2014-05-28clk: st: Terminate of match tableStephen Boyd
2014-05-23clk: st: Fix memory leakValentin Ilie
2014-03-25clk: st: Support for ClockGenA9/DDR/GPUGabriel FERNANDEZ
2014-03-25clk: st: Support for PLLs inside ClockGenA(s)Gabriel FERNANDEZ
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-17 04:58:51 +0000