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Age	Commit message (Expand)	Author
2013-03-21	clk:SPEAr1340: Correct parent clock configuration	Vipul Kumar Samar
2012-12-14	Merge tag 'dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc	Linus Torvalds
2012-11-26	ARM: SPEAr1310: Move 1310 specific misc register into machine specific files	Vipul Kumar Samar
2012-11-21	CLK: SPEAr: Remove unused dummy apb_pclk	Vipul Kumar Samar
2012-11-21	CLK: SPEAr: Correct index scanning done for clock synths	Deepak Sikri
2012-11-21	CLK: SPEAr: Update clock rate table	Deepak Sikri
2012-11-21	CLK: SPEAr: Add missing clocks	Vipul Kumar Samar
2012-11-21	CLK: SPEAr: Set CLK_SET_RATE_PARENT for few clocks	Vipul Kumar Samar
2012-11-21	CLK: SPEAr13xx: fix parent names of multiple clocks	Shiraz Hashim
2012-11-21	CLK: SPEAr13xx: Fix mux clock names	Shiraz Hashim
2012-11-21	CLK: SPEAr: Fix dev_id & con_id for multiple clocks	Rajeev Kumar
2012-11-15	clk: spear: Add stub functions for spear3[0\|1\|2]0_clk_init()	Axel Lin
2012-10-29	clk: SPEAr: Vco-pll: Fix compilation warning	Viresh Kumar
2012-07-18	Clk: SPEAr1340: Update sys clock parent array	Vipul Kumar Samar
2012-07-18	clk: SPEAr1340: Fix clk enable register for uart1 and i2c1.	Vipul Kumar Samar
2012-07-18	Clk:spear6xx:Fix: Rename clk ids within predefined limit	Vipul Kumar Samar
2012-07-18	Clk:spear3xx:Fix: Rename clk ids within predefined limit	Vipul Kumar Samar
2012-07-18	clk:spear1310:Fix: Rename clk ids within predefined limit	Vipul Kumar Samar
2012-07-18	clk:spear1340:Fix: Rename clk ids within predefined limit	Vipul Kumar Samar
2012-06-25	clk: SPEAr600: Fix ethernet clock name for DT based probing	Stefan Roese
2012-06-20	Viresh has moved	Viresh Kumar
2012-05-14	SPEAr13xx: Add common clock framework support	Viresh Kumar
2012-05-12	SPEAr: Switch to common clock framework	Viresh Kumar
2012-05-12	SPEAr: clk: Add General Purpose Timer Synthesizer clock	Viresh Kumar
2012-05-12	SPEAr: clk: Add Fractional Synthesizer clock	Viresh Kumar
2012-05-12	SPEAr: clk: Add Auxiliary Synthesizer clock	Viresh Kumar
2012-05-12	SPEAr: clk: Add VCO-PLL Synthesizer clock	Viresh Kumar