Age | Commit message (Expand) | Author |
---|---|---|
2021-06-27 | clk: agilex/stratix10: add support for the 2nd bypass | Dinh Nguyen |
2021-06-27 | clk: agilex/stratix10: fix bypass representation | Dinh Nguyen |
2021-06-27 | clk: agilex/stratix10: remove noc_clk | Dinh Nguyen |
2021-03-30 | clk: socfpga: Fix code formatting | Stephen Boyd |
2021-03-30 | clk: socfpga: Convert to s10/agilex/n5x to use clk_hw | Dinh Nguyen |
2021-02-12 | clk: socfpga: agilex: add clock driver for eASIC N5X platform | Dinh Nguyen |
2020-09-22 | clk: socfpga: agilex: Remove unused variable 'cntr_mux' | YueHaibing |
2020-06-19 | clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clk | Dinh Nguyen |
2020-06-19 | clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk | Dinh Nguyen |
2020-05-26 | clk: socfpga: agilex: add clock driver for the Agilex platform | Dinh Nguyen |