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clk
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renesas
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r8a77990-cpg-mssr.c
Age
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Author
2020-06-22
clk: renesas: rcar-gen3: Mark RWDT clocks as critical
Ulrich Hecht
2020-02-10
clk: renesas: rcar-gen3: Add CCREE clocks
Geert Uytterhoeven
2019-06-18
clk: renesas: r8a77990: Add CMM clocks
Jacopo Mondi
2019-04-02
clk: renesas: rcar-gen3: Rename DRIF clocks
Takeshi Kihara
2019-04-02
clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC
Takeshi Kihara
2019-04-02
clk: renesas: rcar-gen3: Correct parent clock of HS-USB
Kazuya Mizuguchi
2019-04-02
clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI
Kazuya Mizuguchi
2019-04-02
clk: renesas: r8a77990: Add Z2 clock
Takeshi Kihara
2018-12-04
clk: renesas: r8a77990: Correct parent clock of DU
Takeshi Kihara
2018-09-25
clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment
Geert Uytterhoeven
2018-08-31
clk: renesas: r8a77990: Add missing I2C7 clock
Geert Uytterhoeven
2018-08-27
clk: renesas: r8a77990: Correct RCLK handling
Geert Uytterhoeven
2018-05-09
clk: renesas: cpg-mssr: Add support for R-Car E3
Yoshihiro Shimoda