| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-06-04 | clk: pistachio: Add sanity checks on PLL configuration | Kevin Cernekee |
| 2015-06-04 | clk: pistachio: Lock the PLL when enabled upon rate change | Ezequiel Garcia |
| 2015-06-04 | clk: pistachio: Add a pll_lock() helper for clarity | Ezequiel Garcia |
| 2015-03-31 | CLK: Pistachio: Register external clock gates | Andrew Bresticker |
| 2015-03-31 | CLK: Pistachio: Register system interface gate clocks | Andrew Bresticker |
| 2015-03-31 | CLK: Pistachio: Register peripheral clocks | Andrew Bresticker |
| 2015-03-31 | CLK: Pistachio: Register core clocks | Andrew Bresticker |
| 2015-03-31 | CLK: Pistachio: Add PLL driver | Andrew Bresticker |
| 2015-03-31 | CLK: Add basic infrastructure for Pistachio clocks | Andrew Bresticker |
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index : linux.git | |
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