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Age	Commit message (Expand)	Author
2019-02-13	clk: meson: meson8b: fix the naming of the APB clocks	Martin Blumenstingl
2019-01-07	clk: meson: meson8b: add the GPU clock tree	Martin Blumenstingl
2018-12-03	clk: meson: meson8b: add the read-only video clock trees	Martin Blumenstingl
2018-12-03	clk: meson: meson8b: add the fractional divider for vid_pll_dco	Martin Blumenstingl
2018-11-23	clk: meson: meson8b: add the CPU clock post divider clocks	Martin Blumenstingl
2018-11-23	clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3	Martin Blumenstingl
2018-09-26	clk: meson: clk-pll: remove od parameters	Jerome Brunet
2018-05-18	clk: meson: use SPDX license identifiers consistently	Jerome Brunet
2018-05-15	clk: meson: meson8b: add support for the NAND clocks	Martin Blumenstingl
2018-03-13	clk: meson: add fdiv clock gates	Jerome Brunet
2018-03-13	clk: meson: add mpll pre-divider	Jerome Brunet
2018-03-13	clk: meson: rework meson8b cpu clock	Jerome Brunet
2018-03-13	clk: meson: split divider and gate part of mpll	Jerome Brunet
2017-08-04	clk: meson: meson8b: register the built-in reset controller	Martin Blumenstingl
2017-08-04	clk: meson8b: expose every clock in the bindings	Jerome Brunet
2017-06-12	clk: meson8b: export the ethernet gate clock	Martin Blumenstingl
2017-06-12	clk: meson8b: export the USB clocks	Martin Blumenstingl
2017-06-12	clk: meson8b: export the gate clock for the HW random number generator	Martin Blumenstingl
2017-06-12	clk: meson8b: export the SDIO clock	Martin Blumenstingl
2017-06-12	clk: meson8b: export the SAR ADC clocks	Martin Blumenstingl
2017-03-27	clk: meson8b: add the mplls clocks 0, 1 and 2	Jerome Brunet
2016-09-01	meson: clk: Add support for clock gates	Alexander Müller
2016-09-01	clk: meson: Copy meson8b CLKID defines to private header file	Alexander Müller
2016-09-01	meson: clk: Rename register names according to Amlogic datasheet	Alexander Müller
2016-09-01	meson: clk: Move register definitions to meson8b.h	Alexander Müller