| Age | Commit message (Expand) | Author |
|---|---|---|
| 2017-06-12 | clk: meson8b: export the ethernet gate clock | Martin Blumenstingl |
| 2017-06-12 | clk: meson8b: export the USB clocks | Martin Blumenstingl |
| 2017-06-12 | clk: meson8b: export the gate clock for the HW random number generator | Martin Blumenstingl |
| 2017-06-12 | clk: meson8b: export the SDIO clock | Martin Blumenstingl |
| 2017-06-12 | clk: meson8b: export the SAR ADC clocks | Martin Blumenstingl |
| 2017-03-27 | clk: meson8b: add the mplls clocks 0, 1 and 2 | Jerome Brunet |
| 2016-09-01 | meson: clk: Add support for clock gates | Alexander Müller |
| 2016-09-01 | clk: meson: Copy meson8b CLKID defines to private header file | Alexander Müller |
| 2016-09-01 | meson: clk: Rename register names according to Amlogic datasheet | Alexander Müller |
| 2016-09-01 | meson: clk: Move register definitions to meson8b.h | Alexander Müller |
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index : linux.git | |
| Unnamed repository; edit this file 'description' to name the repository. |
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