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path: root/drivers/clk/meson/meson8b.c
AgeCommit message (Expand)Author
2018-09-26clk: meson: meson8b: use the regmap in the internal reset controllerMartin Blumenstingl
2018-09-26clk: meson: meson8b: register the clock controller earlyMartin Blumenstingl
2018-09-26clk: meson: clk-pll: drop hard-coded rates from pll tablesJerome Brunet
2018-09-26clk: meson: clk-pll: remove od parametersJerome Brunet
2018-09-26clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessaryJerome Brunet
2018-09-26clk: meson: clk-pll: add enable bitJerome Brunet
2018-06-09Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds
2018-05-21clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICALMartin Blumenstingl
2018-05-18clk: meson: use SPDX license identifiers consistentlyJerome Brunet
2018-05-15clk: meson: meson8b: add support for the NAND clocksMartin Blumenstingl
2018-04-25clk: meson: meson8b: fix meson8b_cpu_clk parent clock nameMartin Blumenstingl
2018-04-25clk: meson: meson8b: fix meson8b_fclk_div3_div clock nameMartin Blumenstingl
2018-03-14clk: meson: Drop unused local variable and add staticStephen Boyd
2018-03-13clk: meson: clean-up clk81 clocksJerome Brunet
2018-03-13clk: meson: add fdiv clock gatesJerome Brunet
2018-03-13clk: meson: add mpll pre-dividerJerome Brunet
2018-03-13clk: meson: add fractional part of meson8b fixed_pllJerome Brunet
2018-03-13clk: meson: rework meson8b cpu clockJerome Brunet
2018-03-13clk: meson: split divider and gate part of mpllJerome Brunet
2018-03-13clk: meson: migrate plls clocks to clk_regmapJerome Brunet
2018-03-13clk: meson: migrate mplls clocks to clk_regmapJerome Brunet
2018-03-13clk: meson: migrate muxes to clk_regmapJerome Brunet
2018-03-13clk: meson: migrate dividers to clk_regmapJerome Brunet
2018-03-13clk: meson: migrate gates to clk_regmapJerome Brunet
2018-03-13clk: meson: add regmap to the clock controllersJerome Brunet
2018-03-13clk: meson: remove obsolete commentsJerome Brunet
2018-03-13clk: meson: only one loop index is necessary in probeJerome Brunet
2018-03-13clk: meson: use devm_of_clk_add_hw_providerJerome Brunet
2017-12-14clk: meson: make the spinlock naming more specificYixun Lan
2017-08-23Merge tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson into cl...Stephen Boyd
2017-08-04clk: meson: meson8b: register the built-in reset controllerMartin Blumenstingl
2017-08-04clk: meson: meson8b: fix protection against undefined clksJerome Brunet
2017-08-01clk: meson: mpll: fix mpll0 fractional part ignoredJerome Brunet
2017-06-12clk: meson: meson8b: add compatibles for Meson8 and Meson8m2Martin Blumenstingl
2017-05-29clk: meson: meson8b: mark clk81 as criticalMartin Blumenstingl
2017-03-27clk: meson8b: add the mplls clocks 0, 1 and 2Jerome Brunet
2017-03-27clk: meson8b: put dividers and muxes in tablesJerome Brunet
2017-03-27clk: meson: add missing const qualifiers on gate arraysJerome Brunet
2017-01-26clk: meson8b: fix clk81 register addressJerome Brunet
2016-09-14clk: meson: fix CLKID_GCLK_VENCI_INT typoArnd Bergmann
2016-09-14meson: clk: Use builtin_platform_driver to simplify the codeWei Yongjun
2016-09-01meson: clk: Add support for clock gatesAlexander Müller
2016-09-01clk: meson: Copy meson8b CLKID defines to private header fileAlexander Müller
2016-09-01meson: clk: Rename register names according to Amlogic datasheetAlexander Müller
2016-09-01meson: clk: Move register definitions to meson8b.hAlexander Müller
2016-09-01clk: meson: Rename meson8b-clkc.c to reflect gxbb naming conventionAlexander Müller