| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-03-13 | clk: meson: add fdiv clock gates | Jerome Brunet |
| 2018-03-13 | clk: meson: add mpll pre-divider | Jerome Brunet |
| 2018-03-13 | clk: meson: axg: add hifi pll clock | Jerome Brunet |
| 2018-03-13 | clk: meson: split divider and gate part of mpll | Jerome Brunet |
| 2017-12-14 | clk: meson-axg: add clock controller drivers | Qiufang Dai |
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index : linux.git | |
| Unnamed repository; edit this file 'description' to name the repository. |
| summaryrefslogtreecommitdiff |