Age | Commit message (Expand) | Author |
---|---|---|
2019-06-25 | clk: ingenic: Handle setting the Low-Power Mode bit | Paul Cercueil |
2019-06-07 | clk: ingenic/jz4725b: Fix "pll half" divider not read/written properly | Paul Cercueil |
2019-06-07 | clk: ingenic/jz4725b: Fix incorrect dividers for main clocks | Paul Cercueil |
2019-04-11 | clk: ingenic: jz4725b: Add UDC PHY clock | Paul Cercueil |
2018-10-16 | clk: Add Ingenic jz4725b CGU driver | Paul Cercueil |