| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-05-30 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152 | Thomas Gleixner |
| 2019-04-19 | clk: hi3660: Mark clk_gate_ufs_subsys as critical | Leo Yan |
| 2017-11-14 | clk: hi3660: fix incorrect uart3 clock freqency | Zhong Kaihua |
| 2017-06-19 | clk: hi3660: Set PPLL2 to 2880M | Zhong Kaihua |
| 2017-06-19 | clk: hi3660: add clocks for video encoder, decoder and ISP | Chen Jun |
| 2017-06-19 | clk: hi3660: fix wrong parent name of clk_mux_sysbus | Chen Jun |
| 2017-06-19 | clk: Hi3660: register fixed_rate_clks with CLK_OF_DECLARE_DRIVER | Leo Yan |
| 2017-01-09 | clk: hisilicon: Add clock driver for hi3660 SoC | Zhangfei Gao |
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index : linux.git | |
| Unnamed repository; edit this file 'description' to name the repository. |
| summaryrefslogtreecommitdiff |