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Age	Commit message (Expand)	Author
2020-12-19	clk: at91: sama7g5: register cpu clock	Claudiu Beznea
2020-12-19	clk: at91: clk-master: re-factor master clock	Claudiu Beznea
2020-12-19	clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz	Claudiu Beznea
2020-12-19	clk: at91: sama7g5: decrease lower limit for MCK0 rate	Claudiu Beznea
2020-12-19	clk: at91: sama7g5: remove mck0 from parent list of other clocks	Claudiu Beznea
2020-12-19	clk: at91: clk-sam9x60-pll: allow runtime changes for pll	Claudiu Beznea
2020-12-19	clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics	Eugen Hristev
2020-12-19	clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT	Eugen Hristev
2020-12-19	dt-bindings: clock: at91: add sama7g5 pll defines	Eugen Hristev
2020-12-19	clk: at91: sama7g5: fix compilation error	Claudiu Beznea
2020-07-24	clk: at91: sama7g5: add clock support for sama7g5	Claudiu Beznea