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AgeCommit message (Expand)Author
2019-07-04riscv: remove free_initrd_memChristoph Hellwig
2019-07-04riscv: ccache: Remove unused variableYash Shah
2019-07-03riscv: Introduce huge page support for 32/64bit kernelAlexandre Ghiti
2019-07-01RISC-V: Fix memory reservation in setup_bootmem()Anup Patel
2019-07-01riscv: defconfig: enable SOC_SIFIVELoys Ollivier
2019-07-01riscv: select SiFive platform drivers with SOC_SIFIVELoys Ollivier
2019-07-01arch: riscv: add config option for building SiFive's SoC resourceLoys Ollivier
2019-07-01riscv: Remove gate area stubsAndy Lutomirski
2019-07-01RISC-V: defconfig: Enable NO_HZ_IDLE and HIGH_RES_TIMERSAnup Patel
2019-06-26riscv: mm: Fix code commentShihPo Hung
2019-06-26riscv: dts: Re-organize the DT nodesYash Shah
2019-06-26RISC-V: defconfig: enable MMC & SPI for RISC-VAtish Patra
2019-06-21Merge tag 'spdx-5.2-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/gre...Linus Torvalds
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234Thomas Gleixner
2019-06-17Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netLinus Torvalds
2019-06-17Merge tag 'riscv-for-v5.2/fixes-rc6' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds
2019-06-17riscv: remove unused barrier definesRolf Eike Beer
2019-06-17riscv: mm: synchronize MMU after pte changeShihPo Hung
2019-06-17riscv: dts: add initial board data for the SiFive HiFive UnleashedPaul Walmsley
2019-06-17riscv: dts: add initial support for the SiFive FU540-C000 SoCPaul Walmsley
2019-06-17arch: riscv: add support for building DTB files from DT source dataPaul Walmsley
2019-06-11riscv: Fix udelay in RV32.Nick Hu
2019-06-11riscv: export pm_power_off againAndreas Schwab
2019-06-11RISC-V: defconfig: enable clocks, serial consoleKevin Hilman
2019-06-07Merge git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpfDavid S. Miller
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner
2019-05-31bpf, riscv: clear high 32 bits for ALU32 add/sub/neg/lsh/rsh/arshLuke Nelson
2019-05-30treewide: Add SPDX license identifier - KbuildGreg Kroah-Hartman
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152Thomas Gleixner
2019-05-24treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 120Thomas Gleixner
2019-05-24treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 36Thomas Gleixner
2019-05-23bpf, riscv: clear target register high 32-bits for and/or/xor on ALU32Björn Töpel
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner
2019-05-19Merge tag 'kbuild-v5.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ma...Linus Torvalds
2019-05-19Merge tag 'riscv-for-linus-5.2-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds
2019-05-18arch: remove dangling asm-generic wrappersMasahiro Yamada
2019-05-16riscv: fix locking violation in page fault handlerAndreas Schwab
2019-05-16RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCsYash Shah
2019-05-16RISC-V: Avoid using invalid intermediate translationsPalmer Dabbelt
2019-05-16riscv: Support BUG() in kernel moduleVincent Chen
2019-05-16riscv: Add the support for c.ebreak check in is_valid_bugaddr()Vincent Chen
2019-05-16riscv: support trap-based WARN()Vincent Chen
2019-05-16riscv: fix sbi_remote_sfence_vma{,_asid}.Gary Guo
2019-05-16riscv: move switch_mm to its own fileGary Guo
2019-05-16riscv: move flush_icache_{all,mm} to cacheflush.cGary Guo
2019-05-16RISC-V: Access CSRs using CSR numbersAnup Patel
2019-05-16RISC-V: Add interrupt related SCAUSE defines in asm/csr.hAnup Patel