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Age	Commit message (Expand)	Author
2019-12-27	riscv: export flush_icache_all to modules	Olof Johansson
2019-12-20	riscv: move sifive_l2_cache.c to drivers/soc	Christoph Hellwig
2019-12-04	Merge tag 'riscv/for-v5.5-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel...	Linus Torvalds
2019-11-28	Merge tag 'ioremap-5.5' of git://git.infradead.org/users/hch/ioremap	Linus Torvalds
2019-11-22	Merge branch 'next/misc2' into for-next	Paul Walmsley
2019-11-22	Merge branch 'next/nommu' into for-next	Paul Walmsley
2019-11-22	Merge branch 'next/misc' into for-next	Paul Walmsley
2019-11-22	RISC-V: Add address map dumper	Yash Shah
2019-11-17	riscv: add nommu support	Christoph Hellwig
2019-11-13	riscv: implement remote sfence.i using IPIs	Christoph Hellwig
2019-11-12	riscv: Use PMD_SIZE to replace PTE_PARENT_SIZE	Zong Li
2019-11-11	riscv: use the generic ioremap code	Christoph Hellwig
2019-11-05	riscv: abstract out CSR names for supervisor vs machine mode	Christoph Hellwig
2019-10-29	RISC-V: Issue a tlb page flush if possible	Atish Patra
2019-10-29	RISC-V: Issue a local tlbflush if possible.	Atish Patra
2019-10-29	RISC-V: Do not invoke SBI call if cpumask is empty	Atish Patra
2019-10-28	riscv: add missing header file includes	Paul Walmsley
2019-10-28	riscv: mark some code and data as file-static	Paul Walmsley
2019-10-28	riscv: init: merge split string literals in preprocessor directive	Paul Walmsley
2019-10-28	riscv: add prototypes for assembly language functions from head.S	Paul Walmsley
2019-10-23	riscv: Fix undefined reference to vmemmap_populate_basepages	Kefeng Wang
2019-10-01	riscv: Fix memblock reservation for device tree blob	Albert Ou
2019-09-05	riscv: move the TLB flush logic out of line	Christoph Hellwig
2019-09-05	riscv: cleanup riscv_cpuid_to_hartid_mask	Christoph Hellwig
2019-08-30	RISC-V: Implement sparsemem	Logan Gunthorpe
2019-08-30	riscv: Using CSR numbers to access CSRs	Bin Meng
2019-07-18	Merge tag 'riscv/for-v5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...	Linus Torvalds
2019-07-09	RISC-V: Setup initial page tables in two stages	Anup Patel
2019-07-08	Merge branch 'siginfo-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...	Linus Torvalds
2019-07-04	riscv: remove free_initrd_mem	Christoph Hellwig
2019-07-04	riscv: ccache: Remove unused variable	Yash Shah
2019-07-03	riscv: Introduce huge page support for 32/64bit kernel	Alexandre Ghiti
2019-07-01	RISC-V: Fix memory reservation in setup_bootmem()	Anup Patel
2019-06-26	riscv: mm: Fix code comment	ShihPo Hung
2019-06-17	Merge tag 'riscv-for-v5.2/fixes-rc6' of git://git.kernel.org/pub/scm/linux/ke...	Linus Torvalds
2019-06-17	riscv: mm: synchronize MMU after pte change	ShihPo Hung
2019-06-05	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	Thomas Gleixner
2019-05-29	signal/riscv: Remove tsk parameter from do_trap	Eric W. Biederman
2019-05-24	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 120	Thomas Gleixner
2019-05-21	treewide: Add SPDX license identifier - Makefile/Kconfig	Thomas Gleixner
2019-05-19	Merge tag 'riscv-for-linus-5.2-mw2' of git://git.kernel.org/pub/scm/linux/ker...	Linus Torvalds
2019-05-16	riscv: fix locking violation in page fault handler	Andreas Schwab
2019-05-16	RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs	Yash Shah
2019-05-16	riscv: move switch_mm to its own file	Gary Guo
2019-05-16	riscv: move flush_icache_{all,mm} to cacheflush.c	Gary Guo
2019-05-16	RISC-V: Access CSRs using CSR numbers	Anup Patel
2019-05-14	riscv: switch over to generic free_initmem()	Mike Rapoport
2019-04-10	RISC-V: Fix Maximum Physical Memory 2GiB option for 64bit systems	Anup Patel
2019-03-26	RISC-V: Always compile mm/init.c with cmodel=medany and notrace	Anup Patel
2019-02-21	RISC-V: Free-up initrd in free_initrd_mem()	Anup Patel