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Age	Commit message (Expand)	Author
2019-11-28	Merge tag 'ioremap-5.5' of git://git.infradead.org/users/hch/ioremap	Linus Torvalds
2019-11-17	riscv: add nommu support	Christoph Hellwig
2019-11-11	riscv: use the generic ioremap code	Christoph Hellwig
2019-09-05	riscv: move the TLB flush logic out of line	Christoph Hellwig
2019-07-03	riscv: Introduce huge page support for 32/64bit kernel	Alexandre Ghiti
2019-05-21	treewide: Add SPDX license identifier - Makefile/Kconfig	Thomas Gleixner
2019-05-16	RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs	Yash Shah
2019-05-16	riscv: move switch_mm to its own file	Gary Guo
2019-03-26	RISC-V: Always compile mm/init.c with cmodel=medany and notrace	Anup Patel
2017-11-30	RISC-V: Flush I$ when making a dirty page executable	Andrew Waterman
2017-09-26	RISC-V: Build Infrastructure	Palmer Dabbelt