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Age	Commit message (Expand)	Author
2020-03-16	irqchip/sifive-plic: Enable/Disable external interrupts upon cpu online/offline	Atish Patra
2020-02-18	RISC-V: Don't enable all interrupts in trap_init()	Anup Patel
2019-11-05	riscv: abstract out CSR names for supervisor vs machine mode	Christoph Hellwig
2019-10-28	riscv: for C functions called only from assembly, mark with __visible	Paul Walmsley
2019-10-28	riscv: add missing header file includes	Paul Walmsley
2019-10-25	riscv: cleanup do_trap_break	Christoph Hellwig
2019-10-14	riscv: remove the switch statement in do_trap_break()	Vincent Chen
2019-10-07	riscv: Correct the handling of unexpected ebreak in do_trap_break()	Vincent Chen
2019-10-07	riscv: avoid sending a SIGTRAP to a user thread trapped in WARN()	Vincent Chen
2019-10-07	riscv: avoid kernel hangs when trapped in BUG()	Vincent Chen
2019-07-08	Merge branch 'siginfo-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...	Linus Torvalds
2019-06-05	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	Thomas Gleixner
2019-05-29	signal: Remove the task parameter from force_sig_fault	Eric W. Biederman
2019-05-29	signal: Explicitly call force_sig_fault on current	Eric W. Biederman
2019-05-29	signal/riscv: Remove tsk parameter from do_trap	Eric W. Biederman
2019-05-16	riscv: Support BUG() in kernel module	Vincent Chen
2019-05-16	riscv: Add the support for c.ebreak check in is_valid_bugaddr()	Vincent Chen
2019-05-16	RISC-V: Access CSRs using CSR numbers	Anup Patel
2019-04-25	riscv: remove duplicate macros from ptrace.h	Christoph Hellwig
2018-08-13	RISC-V: Don't increment sepc after breakpoint.	Jim Wilson
2018-06-16	Merge tag 'riscv-for-linus-4.18-merge_window' of git://git.kernel.org/pub/scm...	Linus Torvalds
2018-06-07	riscv: no __user for probe_kernel_address()	Luc Van Oostenryck
2018-04-25	signal/riscv: Replace do_trap_siginfo with force_sig_fault	Eric W. Biederman
2018-04-25	signal/riscv: Use force_sig_fault where appropriate	Eric W. Biederman
2018-04-25	signal: Ensure every siginfo we send has all bits initialized	Eric W. Biederman
2017-09-26	RISC-V: Init and Halt Code	Palmer Dabbelt