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Age	Commit message (Expand)	Author
2019-11-17	riscv: provide native clint access for M-mode	Christoph Hellwig
2019-11-05	riscv: abstract out CSR names for supervisor vs machine mode	Christoph Hellwig
2019-10-28	riscv: add missing header file includes	Paul Walmsley
2019-09-20	RISC-V: Export kernel symbols for kvm	Atish Patra
2019-09-05	riscv: cleanup riscv_cpuid_to_hartid_mask	Christoph Hellwig
2019-09-05	riscv: optimize send_ipi_single	Christoph Hellwig
2019-09-05	riscv: cleanup send_ipi_mask	Christoph Hellwig
2019-09-05	riscv: refactor the IPI code	Christoph Hellwig
2019-06-19	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234	Thomas Gleixner
2019-05-16	riscv: move flush_icache_{all,mm} to cacheflush.c	Gary Guo
2019-05-16	RISC-V: Access CSRs using CSR numbers	Anup Patel
2019-05-16	RISC-V: Fix minor checkpatch issues.	Atish Patra
2019-04-30	RISC-V: Add RISC-V specific arch_match_cpu_phys_id	Atish Patra
2019-03-04	RISC-V: Fixmap support and MM cleanups	Palmer Dabbelt
2019-03-04	RISC-V: Allow hartid-to-cpuid function to fail.	Atish Patra
2019-03-04	RISC-V: Move cpuid to hartid mapping to SMP.	Atish Patra
2019-01-07	riscv: don't stop itself in smp_send_stop	Andreas Schwab
2018-10-22	RISC-V: Show IPI stats	Anup Patel
2018-10-22	RISC-V: Use Linux logical CPU number instead of hartid	Atish Patra
2018-10-22	RISC-V: Add logical CPU indexing for RISC-V	Atish Patra
2018-08-13	RISC-V: simplify software interrupt / IPI code	Christoph Hellwig
2017-12-01	RISC-V: Fixes for clean allmodconfig build	Palmer Dabbelt
2017-11-30	RISC-V: Flush I$ when making a dirty page executable	Andrew Waterman
2017-11-30	RISC-V: Provide stub of setup_profiling_timer()	Olof Johansson
2017-09-26	RISC-V: Init and Halt Code	Palmer Dabbelt