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Age	Commit message (Expand)	Author
2020-07-30	riscv: Cleanup unnecessary define in asm-offset.c	Guo Ren
2020-07-30	riscv: Enable context tracking	Greentime Hu
2020-07-30	riscv: Enable LOCKDEP_SUPPORT & fixup TRACE_IRQFLAGS_SUPPORT	Guo Ren
2020-06-09	RISC-V: Remove do_IRQ() function	Anup Patel
2020-04-09	Merge tag 'riscv-for-linus-5.7' of git://git.kernel.org/pub/scm/linux/kernel/...	Linus Torvalds
2020-03-05	riscv: fix seccomp reject syscall code path	Tycho Andersen
2020-03-03	RISC-V: Inline the assembly register save/restore macros	Palmer Dabbelt
2020-01-28	Merge branch 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/ker...	Linus Torvalds
2019-12-27	riscv: reject invalid syscalls below -1	David Abdurachmanov
2019-12-08	sched/rt, riscv: Use CONFIG_PREEMPTION	Thomas Gleixner
2019-11-22	Merge branch 'next/nommu' into for-next	Paul Walmsley
2019-11-17	riscv: add nommu support	Christoph Hellwig
2019-11-05	riscv: abstract out CSR names for supervisor vs machine mode	Christoph Hellwig
2019-10-29	riscv: add support for SECCOMP and SECCOMP_FILTER	David Abdurachmanov
2019-10-09	RISC-V: entry: Remove unneeded need_resched() loop	Valentin Schneider
2019-10-01	RISC-V: Clear load reservations while restoring hart contexts	Palmer Dabbelt
2019-09-20	riscv: Avoid interrupts being erroneously enabled in handle_exception()	Vincent Chen
2019-08-30	riscv: Using CSR numbers to access CSRs	Bin Meng
2019-06-05	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	Thomas Gleixner
2019-05-16	RISC-V: Access CSRs using CSR numbers	Anup Patel
2019-01-23	RISC-V: Add _TIF_NEED_RESCHED check for kernel thread when CONFIG_PREEMPT=y	Vincent Chen
2019-01-07	riscv: add audit support	David Abdurachmanov
2018-10-22	RISC-V: SMP cleanup and new features	Palmer Dabbelt
2018-10-22	RISC-V: No need to pass scause as arg to do_IRQ()	Anup Patel
2018-10-22	Extract FPU context operations from entry.S	Alan Kao
2018-08-13	RISC-V: implement low-level interrupt handling	Christoph Hellwig
2018-03-14	RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler	Palmer Dabbelt
2018-02-20	RISC-V: Enable IRQ during exception handling	zongbox@gmail.com
2018-01-30	riscv: disable SUM in the exception handler	Christoph Hellwig
2018-01-07	riscv: rename SR_* constants to match the spec	Christoph Hellwig
2017-09-26	RISC-V: Task implementation	Palmer Dabbelt