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Age
Commit message (
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Author
2006-03-24
[PATCH] s/;;/;/g
Alexey Dobriyan
2006-03-22
[PATCH] remove set_page_count() outside mm/
Nick Piggin
2006-03-22
[PATCH] mm: split highorder pages
Nick Piggin
2006-03-21
[MIPS] TX49XX has prefetch.
Atsushi Nemoto
2006-03-21
[MIPS] Kill tlb-andes.c.
Thiemo Seufer
2006-03-21
[MIPS] War on whitespace: cleanup initial spaces followed by tabs.
Ralf Baechle
2006-03-21
[MIPS] Remove CONFIG_BUILD_ELF64.
Ralf Baechle
2006-03-21
[MIPS] sc-rm7k.c cleanup
Atsushi Nemoto
2006-03-18
[MIPS] local_r4k_flush_cache_page fix
Atsushi Nemoto
2006-03-09
[MIPS] Scatter a bunch of __init over tlbex.c.
Ralf Baechle
2006-02-28
[MIPS] Initialize S-cache function pointers even on S-cache-less CPUs.
Ralf Baechle
2006-02-21
[MIPS] Sibyte: #if CONFIG_* doesn't fly.
Ralf Baechle
2006-02-14
[MIPS] Add protected_blast_icache_range, blast_icache_range, etc.
Atsushi Nemoto
2006-02-07
[MIPS] Support /proc/kcore for MIPS
Daniel Jacobowitz
2006-02-07
[MIPS] Remove wrong __user tags.
Atsushi Nemoto
2006-01-10
MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.
Ralf Baechle
2005-12-12
[PATCH] mips: setup_zero_pages count 1
Hugh Dickins
2005-12-01
[MIPS] Use reset_page_mapcount to initialize empty_zero_page usage counter.
Ralf Baechle
2005-10-29
[PATCH] mm: init_mm without ptlock
Hugh Dickins
2005-10-29
SB1 cache exception handling.
Andrew Isaacson
2005-10-29
Add support for SB1A CPU.
Andrew Isaacson
2005-10-29
Fix zero length sys_cacheflush
Atsushi Nemoto
2005-10-29
Rename page argument of flush_cache_page to something more descriptive.
Ralf Baechle
2005-10-29
Fix wrong comment.
Ralf Baechle
2005-10-29
Fixup a few lose ends in explicit support for MIPS R1/R2.
Ralf Baechle
2005-10-29
Don't copy SB1 cache error handler to uncached memory.
Ralf Baechle
2005-10-29
Fix stale comment in c-sb1.c.
Andrew Isaacson
2005-10-29
Cleanup the mess in cpu_cache_init.
Ralf Baechle
2005-10-29
Use R4000 TLB routines for SB1 also.
Ralf Baechle
2005-10-29
Sync c-tx39.c with c-r4k.c.
Atsushi Nemoto
2005-10-29
Add/Fix missing bit of R4600 hit cacheop workaround.
Thiemo Seufer
2005-10-29
Minor code cleanup.
Thiemo Seufer
2005-10-29
R4600 v2.0 needs a nop before tlbp.
Thiemo Seufer
2005-10-29
Don't set up a sg dma address if we have no page address for some reason.
Thiemo Seufer
2005-10-29
More .set push/pop.
Thiemo Seufer
2005-10-29
Let r4600 PRID detection match only legacy CPUs, cleanups.
Thiemo Seufer
2005-10-29
Handle mtc0 - tlb write hazard for VR5432.
Ralf Baechle
2005-10-29
Avoid SMP cacheflushes. This is a minor optimization of startup but
Ralf Baechle
2005-10-29
Philips PNX8550 support: MIPS32-like core with 2 Trimedias on it.
Pete Popov
2005-10-29
More AP / SP bits for the 34K, the Malta bits and things. Still wants
Ralf Baechle
2005-10-29
Mark a few variables __read_mostly.
Ralf Baechle
2005-10-29
MIPS R2 instruction hazard handling.
Ralf Baechle
2005-10-29
Detect the 34K.
Ralf Baechle
2005-10-29
Define kmap_atomic_pfn() for MIPS.
Ralf Baechle
2005-10-29
Date: Fri Jul 8 20:10:17 2005 +0000
Ralf Baechle
2005-10-29
Rename CONFIG_CPU_MIPS{32,64} to CONFIG_CPU_MIPS{32|64}_R1.
Ralf Baechle
2005-10-29
Avoid tlbw* hazards for the R4600/R4700/R5000.
Maciej W. Rozycki
2005-10-29
Inline ioremap() calls for constant addresses that map to KSEG1.
Maciej W. Rozycki
2005-10-29
Fix the diagnostic dump for the XTLB refill handler.
Maciej W. Rozycki
2005-10-29
Fix a diagnostic message.
Maciej W. Rozycki
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