Age | Commit message (Expand) | Author |
---|---|---|
2006-03-21 | [MIPS] TX49XX has prefetch. | Atsushi Nemoto |
2005-10-29 | Add/Fix missing bit of R4600 hit cacheop workaround. | Thiemo Seufer |
2005-10-29 | Let r4600 PRID detection match only legacy CPUs, cleanups. | Thiemo Seufer |
2005-10-29 | Avoid SMP cacheflushes. This is a minor optimization of startup but | Ralf Baechle |
2005-04-16 | Linux-2.6.12-rc2 | Linus Torvalds |